Visible to Intel only — GUID: hco1416490923185
Ixiasoft
Visible to Intel only — GUID: hco1416490923185
Ixiasoft
1.2.5.3. RLDRAM II CIO Pin Utilization for Arria II GZ, Arria V, Stratix III, Stratix IV, and Stratix V Devices
Interface Pin Description |
Memory Device Pin Name |
FPGA Pin Utilization |
---|---|---|
Read Clock |
QK and QK# (1) |
DQS and DQSn pins (S and Sbar in the Intel® Quartus® Prime Pin Planner) |
Data |
Q |
DQ pins (Q in the Intel® Quartus® Prime Pin Planner). Ensure that you are using the DQ pins associated with the chosen read clock pins (DQS and DQSn pins). Intel® FPGA IP does not use the QVLD pin. You may leave this pin unconnected on your board. You may not be able to fit these pins in a DQS group. For more information about how to place these pins, refer to “Exceptions for RLDRAM II and RLDRAM 3 Interfaces” on page 3–34. |
Data Valid |
QVLD |
|
Data Mask |
DM |
|
Write Data Clock |
DK and DK# |
DQ pins in the same DQS group as the read data (Q) pins or in adjacent DQS group or in the same bank as the address and command pins. For more information, refer to Exceptions for RLDRAM II and RLDRAM 3 Interfaces. DK/DK# must use differential output-capable pins. For Nios-based configuration, the DK pins must be in a DQ group but the DK pins do not have to be in the same group as the data or QK pins. |
Memory Clock |
CK and CK# |
Any differential output-capable pins. For Arria V GZ and Stratix V devices, place any unused DQ or DQS pins with DIFFOUT capability. Place the memory clock pins either in the same bank as the DK or DK# pins to improve DK versus CK timing, or in the same bank as the address and command pins to improve address command timing. Do not place CK and CK# pins in the same DQ group as any other DQ or DQS pins. |
Address and Command |
A, BA, CS#, REF#, WE# |
Any user I/O pins. To minimize skew, you should place address and command pins in the same bank or side of the device as the following pins: CK/CK# pins, DQ, DQS, and DM pins. |
Clock source |
— |
Dedicated PLL clock input pin with direct (not using a global clock net) connection to the PLL and optional DLL required by the interface. |
Reset |
— |
Dedicated clock input pin to accommodate the high fan-out signal |
Note to Table:
|