Visible to Intel only — GUID: hco1416491704823
Ixiasoft
Visible to Intel only — GUID: hco1416491704823
Ixiasoft
9.2.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Timing paths
The following table lists all Arria V, Arria V GZ, Cyclone V, and Stratix V devices external memory interface timing paths.
Timing Path |
Circuit Category |
Source |
Destination |
---|---|---|---|
Read Data (2) |
Source‑Synchronous and Calibrated |
Memory DQ, DQS Pins |
DQ Capture Registers in IOE |
Write Data (2) |
Source‑Synchronous and Calibrated |
FPGA DQ, DM, DQS Pins |
Memory DQ, DM, and DQS Pins |
Address and command (2) |
Source-Synchronous |
FPGA CK/CK# and Addr/Cmd Pins |
Memory Input Pins |
Clock-to-Strobe (2) |
Source-Synchronous |
FPGA CK/CK# and DQS Output Pins |
Memory Input Pins |
Read Resynchronization (2) |
Source-Synchronous |
IOE Capture Registers |
Read FIFO in IOE |
PHY & Controller Internal Paths (2) |
Internal Clock fMAX |
Core Registers |
Core Registers |
i/O Toggle Rate (3) |
I/O – Data sheet |
FPGA Output Pin |
Memory Input Pins |
Output Clock Specifications (Jitter, DCD) (4) |
I/O – Data sheet |
FPGA Output Pin |
Memory Input Pins |
Notes to Table:
|