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2.3.1. Terminations for Single-Rank DDR3 SDRAM Unbuffered DIMM
The following table lists the recommended termination and drive strength setting for UDIMM and Stratix III, Stratix IV, and Stratix V FPGA devices.
Signal Type |
SSTL 15 I/O Standard (1) |
FPGA End On-Board Termination (2) |
Memory End Termination for Write |
Memory Driver Strength for Read |
---|---|---|---|---|
DQ |
Class I R50C/G50C (3) |
— |
60-ohm ODT (4) |
40-ohm (4) |
DQS |
Differential Class I R50C/G50C (3) |
— |
60-ohm ODT (4) |
40-ohm (4) |
DM |
Class I R50C (3) |
— |
60-ohm ODT (4) |
40-ohm (4) |
Address and Command |
Class I with maximum drive strength |
— |
39-ohm on-board termination to VDD (5) |
|
CK/CK# |
Differential Class I R50C |
— |
On-board (5) 2.2 pf compensation cap before the first component; 36-ohm termination to VDD for each arm (72-ohm differential); add 0.1 uF just before VDD. |
|
Notes to Table:
|
You can implement a DDR3 SDRAM UDIMM interface in several permutations, such as single DIMM or multiple DIMMs, using either single-ranked or dual‑ranked UDIMMs. In addition to the UDIMM’s form factor, these termination recommendations are also valid for small‑outline (SO) DIMMs and MicroDIMMs.