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Ixiasoft
Visible to Intel only — GUID: hco1416491436911
Ixiasoft
7.2.3.8. Memory Parameters for RLDRAM 3 UniPHY Intel FPGA IP
Use the Memory Timing tab to apply the memory timings from your memory manufacturer’s data sheet.
Parameter |
Description |
---|---|
Enable data-mask pins |
Specifies whether the DM pins of the memory device are driven by the FPGA. |
Data-mask width |
The width of the data-mask on the memory device. |
Data width |
The width of the data bus on the memory device. |
QK width |
The width of the QK (read strobe) bus on the memory device. Select 2 when data width is set to 18. Select 4 when data width is set to 36. |
DK width |
The width of the DK (write strobe) bus on the memory device. For x36 device, DQ[8:0] and DQ[26:18] are referenced to DK0/DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1/DK1#. |
Address width |
The width of the address bus on the memory device. |
Bank-address width |
The width of the bank-address bus on the memory device. |
Burst length |
The burst length supported by the memory device. Refer to memory vendor data sheet. |
tRC |
Mode register bits that set the tRC. Set the tRC according to the memory speed grade and data latency. Refer to the tRC table in the memory vendor data sheet. |
Data Letency |
Mode register bits that set the latency. Set latency according to the interface frequency and memory speed grade. Refer to speed bin table in the memory data sheet. |
Output Drive |
Mode register bits that set the output drive impedance setting. Set the value according to the board simulation. |
ODT |
Mode register bits that set the ODT setting. Set the value according to the board simulation. |
AREF Protocol |
Mode register setting for refreshing memory content of a bank. Select Multibank to allow refresh 4 bank simultaneously. Select Bank Address Control to refresh a particular bank by setting the bank address. |
Write Protocol |
Mode register setting for write protocol. When multiple bank (dual bank or quad bank) is selected, identical data is written to multiple banks. |
Topology |
|
Device width |
Specifies the number of memory devices used for width expansion. |
Parameter |
Description |
---|---|
Memory Device Timing |
|
Maximum memory clock frequency |
The maximum frequency at which the memory device can run. |
tDS (base) |
Base specification for data setup to DK/DK#. Set according to memory speed grade. Refer to memory data sheet. |
tDH (base) |
Base specification for data hold from DK/DK#. Set according to memory speed grade. Refer to memory data sheet. |
tQKQ_max |
QK/QK# clock edge to DQ data edge (in same group). Set according to memory speed grade. Refer to memory data sheet. |
tQH (% of CK) |
DQ output hold time from QK/QK#. Set according to memory speed grade. Refer to memory data sheet. |
tCKDK_max(% of CK) |
Clock to input data clock (max). Set according to memory speed grade. Refer to memory data sheet. |
tCKDK_min (% of CK) |
Clock to input data clock (min). Set according to memory speed grade. Refer to memory data sheet. |
tCKQK_max |
QK edge to clock edge skew (max). Set according to memory speed grade. Refer to memory data sheet. |
tIS (base) |
Base specification for address and control setup to CK.Set according to memory speed grade. Refer to memory data sheet. |
tIH (base) |
Base specification for address and control hold from CK. Set according to memory speed grade. Refer to memory data sheet. |
Controller Timing |
|
Read-to-Write NOP commands (min) |
Minimum number of no operation commands following a read command and before a write command. The value must be at least ((Burst Length/2) + RL - WL + 2). The value, along with other delay/skew parameters, are used by the "Bus Turnaround" timing analysis to determine if bus contention is an issue. Set according to the controller specification. |
Write-to-Read NOP commands (min) |
Minimum number of no operation commands following a write command and before a read command. The value must be at least ((Burst Length/2) + WL - RL + 1). The value, along with other delay/skew parameters, are used by the "Bus Turnaround" timing analysis to determine if bus contention is an issue. Set according to the controller specification. |
RLDRAM 3 Board Derate |
|
CK/CK# slew rate (differential) |
CK/CK# slew rate (differential). |
Address/Command slew rate |
Address and command slew rate. |
DK/DK# slew rate (Differential) |
DK/DK# slew rate (differential). |
DQ slew rate |
DQ slew rate. |
tIS |
Address/command setup time to CK. |