External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Public
Document Table of Contents

1.1.5. DDR, DDR2, and DDR3 SDRAM DIMM Options

Unbuffered DIMMs (UDIMMs) require one set of chip-select (CS#), on-die termination (ODT), clock-enable (CKE), and clock pair (CK/CKn) for every physical rank on the DIMM. Registered DIMMs use only one pair of clocks. DDR3 registered DIMMs require a minimum of two chip-select signals.

Compared to the unbuffered DIMMs (UDIMM), registered and load-reduced DIMMs (RDIMMs and LRDIMMs, respectively) use at least two chip-select signals CS#[1:0] in DDR3. Both RDIMMs and LRDIMMs require an additional parity signal for address, RAS#, CAS#, and WE# signals. The module asserts a parity error signal whenever a parity error is detected.

LRDIMMs expand on the operation of RDIMMs by buffering the DQ/DQS bus. Only one electrical load is presented to the controller regardless of the number of ranks, therefore only one clock enable (CKE) and ODT signal are required for LRDIMMs, regardless of the number of physical ranks. Because the number of physical ranks may exceed the number of physical chip-select signals, DDR3 LRDIMMs provide a feature known as rank multiplication, which aggregates two or four physical ranks into one larger logical rank. Refer to LRDIMM buffer documentation for details on rank multiplication.

The following table shows UDIMM and RDIMM pin options for DDR, DDR2, and DDR3.

Table 2.  UDIMM and RDIMM Pin Options for DDR, DDR2, and DDR3

Pins

UDIMM Pins (Single Rank)

UDIMM Pins

(Dual Rank)

RDIMM Pins (Single Rank)

RDIMM Pins

(Dual Rank)

Data

72 bit DQ[71:0] =

{CB[7:0], DQ[63:0]}

72 bit DQ[71:0] =

{CB[7:0], DQ[63:0]}

72 bit DQ[71:0] =

{CB[7:0], DQ[63:0]}

72 bit DQ[71:0]=

{CB[7:0], DQ[63:0]}

Data Mask

DM[8:0]
DM[8:0]
DM[8:0]
DM[8:0]

Data Strobe  (1)

DQS[8:0] and DQS#[8:0]

DQS[8:0] and DQS#[8:0]

DQS[8:0] and DQS#[8:0]

DQS[8:0] and DQS#[8:0]

Address

BA[2:0], A[15:0]

2 GB: A[13:0]

4 GB: A[14:0]

8 GB: A[15:0]

BA[2:0], A[15:0]

2 GB: A[13:0]

4 GB: A[14:0]

8 GB: A[15:0]

BA[2:0], A[15:0]

2 GB: A[13:0]

4 GB: A[14:0]

8 GB: A[15:0]

BA[2:0], A[15:0]

2 GB: A[13:0]

4 GB: A[14:0]

8 GB: A[15:0]

Clock

CK0/CK0#

CK0/CK0#, CK1/CK1#

CK0/CK0#

CK0/CK0#

Command

ODT, CS#, CKE, RAS#, CAS#, WE#

ODT[1:0], CS#[1:0], CKE[1:0], RAS#, CAS#, WE#

ODT, CS#[1:0], CKE, RAS#, CAS#, WE# 2

ODT[1:0], CS#[1:0], CKE[1:0], RAS#, CAS#, WE#

Parity

PAR_IN, ERR_OUT

PAR_IN, ERR_OUT

Other Pins

SA[2:0], SDA, SCL, EVENT#, RESET#

SA[2:0], SDA, SCL, EVENT#, RESET#

SA[2:0], SDA, SCL, EVENT#, RESET#

SA[2:0], SDA, SCL, EVENT#, RESET#

Note to Table:

  1. DQS#[8:0] is optional in DDR2 SDRAM and is not supported in DDR SDRAM interfaces.
  2. For single rank DDR2 RDIMM, ignore CS#[1] because it is not used.

The following table shows LRDIMM pin options for DDR3.

Table 3.  LRDIMM Pin Options for DDR3

Pins

LRDIMM Pins (x4, 2R)

LRDIMM (x4, 4R, RMF=1) 3

LRDIMM Pins (x4, 4R, RMF=2)

LRDIMM Pins (x4, 8R, RMF=2)

LRDIMM Pins (x4, 8R, RMF=4)

LRDIMM (x8, 4R, RMF=1) 3

LRDIMM Pins (x8, 4R, RMF=2)

Data

72 bit DQ [71:0]=

{CB [7:0], DQ [63:0]}

72 bit DQ [71:0]=

{CB [7:0], DQ [63:0]}

72 bit DQ [71:0]=

{CB [7:0], DQ [63:0]}

72 bit DQ [71:0]=

{CB [7:0], DQ [63:0]}

72 bit DQ [71:0]=

{CB [7:0], DQ [63:0]}

72 bit DQ [71:0]=

{CB [7:0], DQ [63:0]}

72 bit DQ [71:0]=

{CB [7:0], DQ [63:0]}

Data Mask

DM[8:0] DM[8:0]

Data Strobe

DQS[17:0] and DQS#[17:0]

DQS[17:0] and DQS#[17:0]

DQS[17:0] and DQS#[17:0]

DQS[17:0] and DQS#[17:0]

DQS[17:0] and DQS#[17:0]

DQS[8:0] and DQS#[8:0] DQS[8:0] and DQS#[8:0]

Address

BA[2:0], A[15:0]
-2GB:A[13:0]
4GB:A[14:0]
8GB:A[15:0]

BA[2:0], A[15:0]
-2GB:A[13:0]
4GB:A[14:0]
8GB:A[15:0]

BA[2:0], A[16:0]
-4GB:A[14:0]
8GB:A[15:0]
16GB:A[16:0]

BA[2:0], A[16:0]
-4GB:A[14:0]
8GB:A[15:0]
16GB:A[16:0]

  

BA[2:0], A[17:0]
-16GB:A[15:0]
32GB:A[16:0]
64GB:A[17:0]

  

BA[2:0], A[15:0]
-2GB:A[13:0]
4GB:A[14:0]
8GB:A[15:0]

BA[2:0], A[16:0]
-4GB:A[14:0]
8GB:A[15:0]
16GB:A[16:0]

Clock

CK0/CK0#

CK0/CK0#

CK0/CK0#

CK0/CK0#

CK0/CK0#

CK0/CK0#

CK0/CK0#

Command

ODT, CS[1:0]#, CKE, RAS#, CAS#, WE#

ODT, CS[3:0]#, CKE, RAS#, CAS#, WE#

ODT, CS[2:0]#, CKE, RAS#, CAS#, WE#

ODT, CS[3:0]#, CKE, RAS#, CAS#, WE#

ODT, CS[3:0]#, CKE, RAS#, CAS#, WE#

ODT, CS[3:0]#, CKE, RAS#, CAS#, WE#

ODT, CS[2:0]#, CKE, RAS#, CAS#, WE#

Parity

PAR_IN, ERR_OUT

PAR_IN, ERR_OUT

PAR_IN, ERR_OUT

PAR_IN, ERR_OUT

PAR_IN, ERR_OUT

PAR_IN, ERR_OUT

PAR_IN, ERR_OUT

Other Pins

SA[2:0], SDA, SCL, EVENT#, RESET#

SA[2:0], SDA, SCL, EVENT#, RESET#

SA[2:0], SDA, SCL, EVENT#, RESET#

SA[2:0], SDA, SCL, EVENT#, RESET#

SA[2:0], SDA, SCL, EVENT#, RESET#

SA[2:0], SDA, SCL, EVENT#, RESET#

SA[2:0], SDA, SCL, EVENT#, RESET#

Notes to Table:

  1. DM pins are not used for LRDIMMs that are constructed using ×4 components.
  2. S#[2] is treated as A[16] (whose corresponding pins are labeled as CS#[2] or RM[0]) and S#[3] is treated as A[17] (whose corresponding pins are labeled as CS#[3] or RM[1]) for certain rank multiplication configuration.
  3. R = rank, RMF = rank multiplication factor.