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Ixiasoft
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Ixiasoft
1.2.6.2. Number of Enhanced PLL Clock Outputs and Dedicated Clock Outputs Available in Intel® Device Families
Device Family |
Number of Enhanced PLL Clock Outputs |
Number Dedicated Clock Outputs |
---|---|---|
Arria II GX (2) |
7 clock outputs each |
1 single-ended or 1 differential pair 3 single-ended or 3 differential pair total (3) |
Arria V |
18 clock outputs each |
4 single-ended or 2 single-ended and 1 differential pair |
Stratix III |
Left/right: 7 clock outputs Top/bottom: 10 clock outputs |
Left/right: 2 single-ended or 1 differential pair Top/bottom: 6 single-ended or 4 single‑ended and 1 differential pair |
Arria II GZ and Stratix IV |
Left/right: 7 clock outputs Top/bottom: 10 clock outputs |
Left/right: 2 single-ended or 1 differential pair Top/bottom: 6 single-ended or 4 single‑ended and 1 differential pair |
Arria V GZ and Stratix V |
18 clock outputs each |
4 single-ended or 2 single-ended and 1 differential pair |
Notes to Table:
|