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Ixiasoft
9.11. Timing Deration Methodology for Multiple Chip Select DDR2 and DDR3 SDRAM Designs
In the Preset Editor, you must leave the baseline non-derated tDS, tDH, tIS, tIH values, because the settings on the Board Settings page account for multiple chip select slew rate deration.
The following topics explain two timing deration methodologies for multiple chip-select DDR2 and DDR3 SDRAM designs:
- Timing Deration using the Board Settings
- Timing Deration Using the Excel-Based Calculator
For Arria II GX, Arria II GZ, Arria V GZ, Cyclone V, Stratix IV, and Stratix V devices, the UniPHY-based controller parameter editor has an option to select multiple chip-select deration.
Timing deration in this section applies to either discrete components or DIMMs.
This section assumes you know how to obtain data on PCB simulations for timing deration from HyperLynx or any other PCB simulator.