Visible to Intel only — GUID: wjr1505149424351
Ixiasoft
Visible to Intel only — GUID: wjr1505149424351
Ixiasoft
1.1.16.3. Maximum Number of DDR3 SDRAM Interfaces Supported per FPGA
Each interface of size n, where n is a multiple of 8, consists of:
- n DQ pins (including ECC)
- n/8 DM pins
- n/8 DQS, DQSn pin pairs
- 17 address pins
- 7 command pins (CAS#, RAS#, WE#, CKE, ODT, reset, and CS#)
- 1 CK, CK# pin pair
Device |
Device Type |
Package Pin Count |
Maximum Number of Interfaces |
---|---|---|---|
Arria II GX |
EP2AGX190 EP2AGX260 |
1,152 |
|
EP2AGX45 EP2AGX65 |
358 |
|
|
Arria II GZ |
EP2AGZ300 EP2AGZ350 EP2AGZ225 |
1,517 |
Four ×8 interfaces on each side |
EP2AGZ300 EP2AGZ350 |
780 |
|
|
Arria V |
5AGXB1 5AGXB3 5AGXB5 5AGXB7 5AGTD3 5AGTD7 |
1,517 |
|
5AGXA1 5AGXA3 |
672 |
|
|
5AGXA5 5AGXA7 |
672 |
|
|
Arria V GZ |
5AGZE5 5AGZE7 |
1,517 |
|
5AGZE1 5AGZE3 |
780 |
|
|
Cyclone V |
5CGTD9 5CEA9 5CGXC9 |
1,152 |
|
5CEA7 5CGTD7 5CGXC7 |
484 |
|
|
MAX 10 FPGA |
10M50D672 10M40D672 |
762 |
One x32 interface on the right side |
10M50D256 10M40D256 10M25D256 10M16D256 |
256 |
One x8 interface on the right side |
|
Stratix III |
EP3SL340 |
1,760 |
|
EP3SE50 |
484 |
|
|
Stratix IV |
EP4SGX290 EP4SGX360 EP4SGX530 |
1,932 |
or
|
EP4SE530 EP4SE820 |
1,760 |
||
EP4SGX70 EP4SGX110 EP4SGX180 EP4SGX230 |
780 |
|
|
Stratix V |
5SGXA5 5SGXA7 |
1,932 |
|
5SGXA3 5SGXA4 |
780 |
|
Refer also to the EMIF Device Selector, which is available from the Device Selection option of the External Memory Interfaces IP - Support Center page on the Intel® website.