Visible to Intel only — GUID: hco1416491741440
Ixiasoft
Visible to Intel only — GUID: hco1416491741440
Ixiasoft
9.4.1.6. DQS versus CK—Arria II GX and Cyclone IV Devices
There are two timing constraints for DQS versus CK timing path to account for duty cycle distortion. The DQS/DQS# rising edge to CK/CK# rising edge (tDQSS) requires the rising edge of DQS to align with the rising edge of CK to within 25% of a clock cycle, while the DQS/DQS# falling edge setup/hold time from CK/CK# rising edge (tDSS/tDSH) requires the falling edge of DQS to be more than 20% of a clock cycle away from the rising edge of CK.
The Timing Analyzer analyzes the DQS vs CK timing paths using the set_output_delay (max and min) constraints. For more information, refer to <phy_variation_name> _phy_ddr_timing.sdc.