Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide

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ID 814550
Date 5/24/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash U4 with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing Quartus® Prime Software 4.1.5. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. Diagnostic GUI 4.3.2. Clock Controller GUI 4.3.3. Power Monitor GUI 4.3.4. MAX® 10 Controller GUI 4.3.5. Agilex™ 5 FPGA E-Series Test Functionality 4.3.6. Information Display
4.3.2. Clock Controller GUI x
4.3.2.1. Si5332 Clock 4.3.2.2. Si5518 Clock
4.3.3. Power Monitor GUI x
4.3.3.1. Power Monitor 4.3.3.2. Temperature Monitor
4.3.4. MAX® 10 Controller GUI x
4.3.4.1. Remote I/O Control 4.3.4.2. Expansion Board Control 4.3.4.3. System Control
4.3.4.1. Remote I/O Control x
4.3.4.1.1. Remote Control 4.3.4.1.2. MISC LED Control
4.3.4.1.1. Remote Control x
4.3.4.1.1.1. Push Button 4.3.4.1.1.2. User Switch 4.3.4.1.1.3. MSEL 4.3.4.1.1.4. Si569-1V8
4.3.5. Agilex™ 5 FPGA E-Series Test Functionality x
4.3.5.1. DDR4 Test 4.3.5.2. HPS DDR4 Test 4.3.5.3. LPDDR4 Test 4.3.5.4. QSFP Test 4.3.5.5. SFP+ Test 4.3.5.6. FMC+ Test 4.3.5.7. SMA Test
4.3.6. Information Display x
4.3.6.1. Sys Info 4.3.6.2. Connection 4.3.6.3. The Bottom Status Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.3. Configuring the FPGA Device by Avalon® Streaming Modes 5.4. Expansion Boards
5.4. Expansion Boards x
5.4.1. HPS Expansion Board (HPS-EB) 5.4.2. HPS NAND Board (HPS-NB) 5.4.3. HPS Test Board (HPS-TB)
6. Custom Projects for the Development Kit x
6.1. Golden Top
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Input and Output Components A.7. Memory Interfaces A.8. Communication Interfaces A.9. Expansion Boards A.10. Connectors and Headers
A.2. System Management x
A.2.1. JTAG Master Sources
A.6. Input and Output Components x
A.6.1. Push Buttons A.6.2. Switches A.6.3. LEDs
A.8. Communication Interfaces x
A.8.1. QSFP+ A.8.2. SFP+ A.8.3. Ethernet A.8.4. FMC A.8.5. MIPI A.8.6. USB3.1 A.8.7. HPS IO48 Interface A.8.8. Serial Buses
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.6.2. Switches

The Agilex™ 5 FPGA E-Series 065B Premium Development Kit includes user-controlled switches for various features on the board.
Table 12.  Switches
Board Reference Schematic Signal Name Description
SW16.1 SW_USER_IMAGE_SEL
  • ON to select user image
  • OFF to select factory image
SW16.2 SW_HPS_JTAG_BYPASS
  • ON to bypass HPS JTAG chain
  • OFF to enable HPS JTAG chain
SW16.3 USB_MAX_JTAG_SEL
  • ON to select embedded Intel® FPGA Download Cable II
  • OFF to select external Intel® FPGA Download Cable II dongle
SW16.4 SW_FMC_JTAG_BYPASS
  • ON to bypass FMC JTAG chain
  • OFF to enable FMC JTAG chain
SW21.1 FPGA_USER_SW1 User switch 1
SW21.2 FPGA_USER_SW2 User switch 2
SW21.3 FPGA_USER_SW3 User switch 3
SW21.4 FPGA_USER_SW4 User switch 4
SW22 POWER_ON ON/OFF development kit
SW23 RS232_SEL
  • ON to select the RS232 path from the external header
  • OFF to select the RS232 path from the USB connector
SW24.1 HSIO_IO1
  • ON to connect HSIO_IO1 to ground
  • OFF to open HSIO_IO1
SW24.2 HSIO_IO2
  • ON to connect HSIO_IO2 to ground
  • OFF to open HSIO_IO2
SW24.3 HSIO_IO3
  • ON to connect HSIO_IO3 to ground
  • OFF to open HSIO_IO3
SW24.4 HSIO_IO4
  • ON to connect HSIO_IO4 to ground
  • OFF to open HSIO_IO4
SW25 88E2110_ENET1_CONFIG0 Configures the 88E2110 ENET1 PHYAD setting.
SW27.1 SWITCH_MSEL0 Configures MSEL0.
SW27.2 SWITCH_MSEL1 Configures MSEL1.
SW27.3 SWITCH_MSEL2 Configures MSEL2.
SW27.4 SWITCH_SI569_FS Selects FMC VCXO REFCLK frequency.

You can use the remote control to control the user switch (SW21[1:4]) and MSEL configuration switch (SW27[1:4]) through BTS. The remote control overrides the state of the physical switch when enabled.

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