Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide

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ID 814550
Date 5/24/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash U4 with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing Quartus® Prime Software 4.1.5. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. Diagnostic GUI 4.3.2. Clock Controller GUI 4.3.3. Power Monitor GUI 4.3.4. MAX® 10 Controller GUI 4.3.5. Agilex™ 5 FPGA E-Series Test Functionality 4.3.6. Information Display
4.3.2. Clock Controller GUI x
4.3.2.1. Si5332 Clock 4.3.2.2. Si5518 Clock
4.3.3. Power Monitor GUI x
4.3.3.1. Power Monitor 4.3.3.2. Temperature Monitor
4.3.4. MAX® 10 Controller GUI x
4.3.4.1. Remote I/O Control 4.3.4.2. Expansion Board Control 4.3.4.3. System Control
4.3.4.1. Remote I/O Control x
4.3.4.1.1. Remote Control 4.3.4.1.2. MISC LED Control
4.3.4.1.1. Remote Control x
4.3.4.1.1.1. Push Button 4.3.4.1.1.2. User Switch 4.3.4.1.1.3. MSEL 4.3.4.1.1.4. Si569-1V8
4.3.5. Agilex™ 5 FPGA E-Series Test Functionality x
4.3.5.1. DDR4 Test 4.3.5.2. HPS DDR4 Test 4.3.5.3. LPDDR4 Test 4.3.5.4. QSFP Test 4.3.5.5. SFP+ Test 4.3.5.6. FMC+ Test 4.3.5.7. SMA Test
4.3.6. Information Display x
4.3.6.1. Sys Info 4.3.6.2. Connection 4.3.6.3. The Bottom Status Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.3. Configuring the FPGA Device by Avalon® Streaming Modes 5.4. Expansion Boards
5.4. Expansion Boards x
5.4.1. HPS Expansion Board (HPS-EB) 5.4.2. HPS NAND Board (HPS-NB) 5.4.3. HPS Test Board (HPS-TB)
6. Custom Projects for the Development Kit x
6.1. Golden Top
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Input and Output Components A.7. Memory Interfaces A.8. Communication Interfaces A.9. Expansion Boards A.10. Connectors and Headers
A.2. System Management x
A.2.1. JTAG Master Sources
A.6. Input and Output Components x
A.6.1. Push Buttons A.6.2. Switches A.6.3. LEDs
A.8. Communication Interfaces x
A.8.1. QSFP+ A.8.2. SFP+ A.8.3. Ethernet A.8.4. FMC A.8.5. MIPI A.8.6. USB3.1 A.8.7. HPS IO48 Interface A.8.8. Serial Buses
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.9. Expansion Boards

HPS Expansion Board

  • RGMII 10/100/1000 Mbps Ethernet port
  • UART port: Standard USB Mini-B Receptacle
  • Micro SD Card Connector
  • Type C USB connector
  • Mictor* 38-pin connector (JTAG only without Trace signals)
  • I3C header
Table 26.  HPS IO48 Pinout
IO48 Interface Type Signal Name I/O Direction1
IOA01 CM HPS_OSC_CLK i
IOA02 ENET_INTn IO11 o
IOA03 UART0 TX o
IOA04 UART0 RX i
IOA05 EMAC2 PPS2 o
IOA06 EMAC2 PPSTRIG2 i
IOA07 MDIO2 MDIO b
IOA08 MDIO2 MDC o
IOA09 I3C1 SDA b
IOA10 I3C1 SCL b
IOA11 LED1 IO10 o
IOA12 LED2 IO11 o
IOA13 USB1 CLK i
IOA14 USB1 STEP o
IOA15 USB1 DIR i
IOA16 USB1 DATA0 b
IOA17 USB1 DATA1 b
IOA18 USB1 NXT i
IOA19 USB1 DATA2 b
IOA20 USB1 DATA3 b
IOA21 USB1 DATA4 b
IOA22 USB1 DATA5 b
IOA23 USB1 DATA6 b
IOA24 USB1 DATA7 b
IOB01 SDMMC DATA0 b
IOB02 SDMMC DATA1 b
IOB03 SDMMC CLK o
IOB04 PB2 IO3 i
IOB05 PB1 IO4 i
IOB06 SDMMC DATA2 b
IOB07 SDMMC DATA3 b
IOB08 SDMMC CMD o
IOB09 JTAG TCK i
IOB10 JTAG TMS i
IOB11 JTAG TDO o
IOB12 JTAG TDI i
IOB13 EMAC2 TX_CLK o
IOB14 EMAC2 TX_CTL o
IOB15 EMAC2 RX_CLK i
IOB16 EMAC2 RX_CTL i
IOB17 EMAC2 TXD0 o
IOB18 EMAC2 TXD1 o
IOB19 EMAC2 RXD0 i
IOB20 EMAC2 RXD1 i
IOB21 EMAC2 TXD2 o
IOB22 EMAC2 TXD3 o
IOB23 EMAC2 RXD2 i
IOB24 EMAC2 RXD3 i
1 The signal direction is viewed at the Agilex™ 5 FPGA HPS IO48 I/O sides.
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