Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide

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ID 814550
Date 8/05/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Installing the HPS Expansion Board (HPS-EB) 3.2. Default Settings 3.3. Powering Up the Development Kit 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U10 with Default Factory Image 3.4.2. Restoring Board QSPI Flash U4 with Default Factory Image 3.4.3. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Installing Quartus® Prime Software 4.1.2. Setting Up the Programmer 4.1.3. Running the BTS GUI on Windows 4.1.4. Running the BTS GUI on Linux
4.1.4. Running the BTS GUI on Linux x
4.1.4.1. Configuring the Linux UART Environment 4.1.4.2. Launching the BTS
4.3. BTS Functionalities x
4.3.1. Diagnostic GUI 4.3.2. Clock Controller GUI 4.3.3. Power Monitor GUI 4.3.4. MAX® 10 Controller GUI 4.3.5. Agilex™ 5 FPGA Functionality 4.3.6. Information Display 4.3.7. Migrating Development Kit Installer Package from v24.1 to v24.2
4.3.2. Clock Controller GUI x
4.3.2.1. Si5332 Clock 4.3.2.2. Si5518 Clock
4.3.3. Power Monitor GUI x
4.3.3.1. Power Monitor 4.3.3.2. Temperature Monitor
4.3.4. MAX® 10 Controller GUI x
4.3.4.1. Remote I/O Control 4.3.4.2. Expansion Board Control 4.3.4.3. System Control
4.3.4.1. Remote I/O Control x
4.3.4.1.1. Remote Control 4.3.4.1.2. MISC LED Control
4.3.4.1.1. Remote Control x
4.3.4.1.1.1. Push Button 4.3.4.1.1.2. User Switch 4.3.4.1.1.3. MSEL 4.3.4.1.1.4. Si569-1V8
4.3.5. Agilex™ 5 FPGA Functionality x
4.3.5.1. The GPIO Tab 4.3.5.2. The Memory Tab 4.3.5.3. The Transceiver Tab
4.3.5.2. The Memory Tab x
4.3.5.2.1. The DDR4 COMP Tab 4.3.5.2.2. The HPS DDR4 COMP Tab 4.3.5.2.3. The LPDDR4 COMP Tab
4.3.5.3. The Transceiver Tab x
4.3.5.3.1. QSFP Test 4.3.5.3.2. SFP+ Test 4.3.5.3.3. FMC+ Test 4.3.5.3.4. SMA Test
4.3.6. Information Display x
4.3.6.1. Sys Info 4.3.6.2. Connection 4.3.6.3. The Bottom Status Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.3. Configuring the FPGA Device by Avalon® Streaming Modes 5.4. Expansion Boards
5.4. Expansion Boards x
5.4.1. HPS Expansion Board (HPS-EB) 5.4.2. HPS NAND Board (HPS-NB) 5.4.3. HPS Test Board (HPS-TB)
5.4.1. HPS Expansion Board (HPS-EB) x
5.4.1.1. Booting from SD Card using HPS Enablement DC
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Input and Output Components A.7. Memory Interfaces A.8. Communication Interfaces A.9. Expansion Boards A.10. Connectors and Headers
A.2. System Management x
A.2.1. JTAG Master Sources
A.6. Input and Output Components x
A.6.1. Push Buttons A.6.2. Switches A.6.3. LEDs
A.8. Communication Interfaces x
A.8.1. QSFP+ A.8.2. SFP+ A.8.3. Ethernet A.8.4. FMC A.8.5. MIPI A.8.6. USB3.1 A.8.7. HPS IO48 Interface A.8.8. Serial Buses
A.9. Expansion Boards x
A.9.1. HPS Expansion Board (HPS-EB) A.9.2. HPS NAND Board (HPS-NB) A.9.3. HPS Test Board (HPS-TB) HPS Test Board (HPS-TB)
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.9.3. HPS Test Board (HPS-TB)

HPS Test Board (HPS-TB)

  • RGMII 10/100/1000 Mbps Ethernet port
  • UART port: Standard USB Mini-B Receptacle
  • Micro SD card connector
  • Type C USB connector
  • Mictor* 38-pin connector (JTAG only without Trace signals)
  • I3C header
Table 29.  HPS IO48 Pinout for HPS Test Board (HPS-TB)
IO48 Interface Type Signal Name I/O Direction5
IOA01 EMAC0 PPS0 o
IOA02 EMAC0 PPSTRIG0 i
IOA03 UART0 TX o
IOA04 UART0 RX i
IOA05 SPIM0 CLK o
IOA06 SPIM0 MOSI o
IOA07 SPIM0 MISO i
IOA08 SPIM0 SS0_N o
IOA09 I3C1 SDA b
IOA10 I3C1 SCL b
IOA11 MDIO0 MDIO b
IOA12 MDIO0 MDC o
IOA13 EMAC0 TX_CLK o
IOA14 EMAC0 TX_CTL o
IOA15 EMAC0 RX_CLK i
IOA16 EMAC0 RX_CTL i
IOA17 EMAC0 TXD0 o
IOA18 EMAC0 TXD1 o
IOA19 EMAC0 RXD0 i
IOA20 EMAC0 RXD1 i
IOA21 EMAC0 TXD2 o
IOA22 EMAC0 TXD3 o
IOA23 EMAC0 RXD2 i
IOA24 EMAC0 RXD3 i
IOB01 SDMMC DATA0 b
IOB02 SDMMC DATA1 b
IOB03 SDMMC CLK o
IOB04 Lvl_Shift_Sel IO3 o
IOB05 PB0 IO4 i
IOB06 SDMMC DATA2 b
IOB07 SDMMC DATA3 b
IOB08 SDMMC CMD o
IOB09 JTAG TCK i
IOB10 JTAG TMS i
IOB11 JTAG TDO o
IOB12 JTAG TDI i
IOB13 LED1/SDMMC IO4/PU_PD_DATA2 o
IOB14 ENET_INTn IO2 i
IOB15 CM HPS_OSC_CLK i
IOB16 Trace D7 o
IOB17 Trace D6 o
IOB18 Trace D5 o
IOB19 Trace D4 o
IOB20 Trace CLK o
IOB21 Trace D0 o
IOB22 Trace D1 o
IOB23 Trace D2 o
IOB24 Trace D3 o
5 The signal direction is viewed at the Agilex™ 5 FPGA HPS IO48 I/O sides.
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