Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide

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ID 814550
Date 5/24/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash U4 with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing Quartus® Prime Software 4.1.5. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. Diagnostic GUI 4.3.2. Clock Controller GUI 4.3.3. Power Monitor GUI 4.3.4. MAX® 10 Controller GUI 4.3.5. Agilex™ 5 FPGA E-Series Test Functionality 4.3.6. Information Display
4.3.2. Clock Controller GUI x
4.3.2.1. Si5332 Clock 4.3.2.2. Si5518 Clock
4.3.3. Power Monitor GUI x
4.3.3.1. Power Monitor 4.3.3.2. Temperature Monitor
4.3.4. MAX® 10 Controller GUI x
4.3.4.1. Remote I/O Control 4.3.4.2. Expansion Board Control 4.3.4.3. System Control
4.3.4.1. Remote I/O Control x
4.3.4.1.1. Remote Control 4.3.4.1.2. MISC LED Control
4.3.4.1.1. Remote Control x
4.3.4.1.1.1. Push Button 4.3.4.1.1.2. User Switch 4.3.4.1.1.3. MSEL 4.3.4.1.1.4. Si569-1V8
4.3.5. Agilex™ 5 FPGA E-Series Test Functionality x
4.3.5.1. DDR4 Test 4.3.5.2. HPS DDR4 Test 4.3.5.3. LPDDR4 Test 4.3.5.4. QSFP Test 4.3.5.5. SFP+ Test 4.3.5.6. FMC+ Test 4.3.5.7. SMA Test
4.3.6. Information Display x
4.3.6.1. Sys Info 4.3.6.2. Connection 4.3.6.3. The Bottom Status Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.3. Configuring the FPGA Device by Avalon® Streaming Modes 5.4. Expansion Boards
5.4. Expansion Boards x
5.4.1. HPS Expansion Board (HPS-EB) 5.4.2. HPS NAND Board (HPS-NB) 5.4.3. HPS Test Board (HPS-TB)
6. Custom Projects for the Development Kit x
6.1. Golden Top
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Input and Output Components A.7. Memory Interfaces A.8. Communication Interfaces A.9. Expansion Boards A.10. Connectors and Headers
A.2. System Management x
A.2.1. JTAG Master Sources
A.6. Input and Output Components x
A.6.1. Push Buttons A.6.2. Switches A.6.3. LEDs
A.8. Communication Interfaces x
A.8.1. QSFP+ A.8.2. SFP+ A.8.3. Ethernet RGMII (IO48 HPS) RGMII (HVIO Bank 6D) SGMII (Transceiver Bank 1C) A.8.4. FMC A.8.5. MIPI A.8.6. USB3.1 A.8.7. HPS IO48 Interface A.8.8. Serial Buses
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.8.3. Ethernet

The Agilex™ 5 FPGA E-Series 065B Premium Development Kit supports three Ethernet configurations.
Table 18.  Ethernet Configuration
Index Interface Configuration Supported Rates External PHY Connector Reference
1 RGMII (via HPS pins) 10M/100M/1G Marvell* 88E1512 J5 (on HPS card)
2 RGMII (via FPGA HVIO pins) 10M/100M/1G Marvell 88E1512 J42
3 SGMII (via FPGA XCVR pins) 10M/100M/1G/2.5G Marvell 88E2110 J41

RGMII (IO48 HPS)

The Agilex™ 5 FPGA E-Series 065B Premium Development Kit provides one 10M/100M/1G RGMII interface through the IO48 HPS interface. The Marvell 88E1512 and connector J5 are mounted on the HPS card.

RGMII (HVIO Bank 6D)

The Agilex™ 5 FPGA E-Series 065B Premium Development Kit provides one 10M/100M/1G RGMII interface through the HVIO interface. The Marvell 88E1512 and connector J42 are mounted on the development kit.

Table 19.  RGMII via FPGA HVIO
Schematic Signal Name Description
88E1512_RGMII_RXCTL RGMII receive control signal
88E1512_RGMII_RXCLK RGMII receive clock
88E1512_RGMII_TXCTL RGMII transmit control signal
88E1512_RGMII_TXCLK RGMII transmit clock
88E1512_RGMII_TXD[0:3] RGMII transmit data
88E1512_RGMII_RXD[0:3] RGMII receive data
88E1512_MDC Management data clock reference
88E1512_MDIO Management data
88E1512_RESETN 88E2110 reset pin
88E1512_LED2_INTN LED[2] pin or interrupt output pin

SGMII (Transceiver Bank 1C)

The Agilex™ 5 FPGA E-Series 065B Premium Development Kit provides one 10M/100M/1G/2.5G SGMII interface. The transmit and receive data are connected to the transceiver interface. Other control signals are connected to Bank 5B. The Marvell 88E2110 and connector J41 are mounted on the development kit.

Table 20.  SGMII via FPGA XCVR
Schematic Signal Name Description
88E2110_SGMII_ENET1_TXP/N SGMII transmit data
88E2110_SGMII_ENET1_RXP/N SGMII receive data
88E2210_ENET1_MDC Management data clock reference
88E2210_ENET1_MDIO Management data
88E2110_ENET1_RESETN 88E1512 reset pin
88E2210_ENET1_INTN Interrupt output pin
Level Two Title