Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide

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ID 814550
Date 5/24/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash U4 with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing Quartus® Prime Software 4.1.5. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. Diagnostic GUI 4.3.2. Clock Controller GUI 4.3.3. Power Monitor GUI 4.3.4. MAX® 10 Controller GUI 4.3.5. Agilex™ 5 FPGA E-Series Test Functionality 4.3.6. Information Display
4.3.2. Clock Controller GUI x
4.3.2.1. Si5332 Clock 4.3.2.2. Si5518 Clock
4.3.3. Power Monitor GUI x
4.3.3.1. Power Monitor 4.3.3.2. Temperature Monitor
4.3.4. MAX® 10 Controller GUI x
4.3.4.1. Remote I/O Control 4.3.4.2. Expansion Board Control 4.3.4.3. System Control
4.3.4.1. Remote I/O Control x
4.3.4.1.1. Remote Control 4.3.4.1.2. MISC LED Control
4.3.4.1.1. Remote Control x
4.3.4.1.1.1. Push Button 4.3.4.1.1.2. User Switch 4.3.4.1.1.3. MSEL 4.3.4.1.1.4. Si569-1V8
4.3.5. Agilex™ 5 FPGA E-Series Test Functionality x
4.3.5.1. DDR4 Test 4.3.5.2. HPS DDR4 Test 4.3.5.3. LPDDR4 Test 4.3.5.4. QSFP Test 4.3.5.5. SFP+ Test 4.3.5.6. FMC+ Test 4.3.5.7. SMA Test
4.3.6. Information Display x
4.3.6.1. Sys Info 4.3.6.2. Connection 4.3.6.3. The Bottom Status Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.3. Configuring the FPGA Device by Avalon® Streaming Modes 5.4. Expansion Boards
5.4. Expansion Boards x
5.4.1. HPS Expansion Board (HPS-EB) 5.4.2. HPS NAND Board (HPS-NB) 5.4.3. HPS Test Board (HPS-TB)
6. Custom Projects for the Development Kit x
6.1. Golden Top
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Input and Output Components A.7. Memory Interfaces A.8. Communication Interfaces A.9. Expansion Boards A.10. Connectors and Headers
A.2. System Management x
A.2.1. JTAG Master Sources
A.6. Input and Output Components x
A.6.1. Push Buttons A.6.2. Switches A.6.3. LEDs
A.8. Communication Interfaces x
A.8.1. QSFP+ A.8.2. SFP+ A.8.3. Ethernet A.8.4. FMC A.8.5. MIPI A.8.6. USB3.1 A.8.7. HPS IO48 Interface A.8.8. Serial Buses
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.4. Clocks

Table 8.  Onboard Clock Sources
Source Signal Name Default Frequency I/O Standard Application
U67 (SI5518) 1PPS_3V3_SI5518_TO_FPGA 1 Hz LVCMOS 3.3 V 1PPS to FPGA
1PPS_GRAND_MASTER_LOOPBACK 1 Hz LVCMOS 3.3 V 1PPS loopback to SI5518
PTP_SAMPLE_CLK_250M_P/N 250 MHz LVDS 3.3 V PTP sample clock
TOD_MASTER_CLK_125M_P/N 125 MHz LVDS 3.3 V ToD master clock
CIPRI_HIGH_REFCLK_P/N 184.32 MHz LVDS 3.3 V CIPRI High clock
CIPRI_LOW_REFCLK_P/N 153.6 MHz LVDS 3.3 V CIPRI Low clock
5518_QSFP1_REFCLK_P/N 156.25 MHz LVDS 3.3 V QSFP1 clock
QSFP2_REFCLK_P/N 156.25 MHz LVDS 3.3 V QSFP2 clock
HVIO6D_PLLREFCLK1 125 MHz LVCMOS 1.8 V HVIO 6D Bank PLL clock
HVIO5B_PLLREFCLK2 100 MHz LVCMOS 3.3 V HVIO 5B Bank PLL clock
USB3_REFCLK_P/N 100 MHz LVDS 3.3 V USB3 clock
U411 (SI5332) 5332_SFP_REFCLK_P/N 156.25 MHz LVDS 1.8 V SFP clock
LPDDR4_REFCLK_P/N 116.625 MHz LVDS 1.8 V LPDDR4 clock
RESERVE_FMC_PCIE_REFCLK_P/N 100 MHz LVDS 1.8 V FMC REFCLK_C2M clock (reserved)
HVIO6C_PLLREFCLK1 100 MHz LVCMOS 3.3 V HVIO 6C Bank PLL clock
HVIO5B_SYSPLLREFCLK_L1A_0 100 MHz LVCMOS 3.3 V HVIO 5B Bank SYSPLL clock
U412 (SI5332) 88E2110_REFCLK_P/N 125 MHz LVDS 3.3 V 88E2110 clock
DDR4_COMP1_REFCLK_P/N 100 MHz LVDS 1.8 V DDR4 COMP1 clock
DDR4_COMP_REFCLK_P/N 100 MHz LVDS 1.8 V DDR4 COMP clock
MIPI_REFCLK_P/N 100 MHz LVDS 3.3 V MIPI clock
SMA_CLKOUT_P/N 100 MHz LVDS 3.3 V SMA clock out (J30/J31)
U2 (SI510 XTAL) MAX10_50M_CLK 50 MHz LVCMOS 3.3 V MAX® 10 clock
U12 (SI510 XTAL) FPGA_OSC_CLK1 125 MHz LVCMOS 1.8 V FPGA SDM clock
X5 (SI569 VCXO) FMC_VCXO_REFCLK_P/N 148.35 MHz LVDS 2.5 V FMC/HDMI clock
X6 (SI548 XO) FMC_PROG_REFCLK_P/N 135 MHz LVDS 2.5 V FMC/DP clock
Figure 53. Clock Tree
Level Two Title