Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide

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ID 814550
Date 8/05/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Installing the HPS Expansion Board (HPS-EB) 3.2. Default Settings 3.3. Powering Up the Development Kit 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U10 with Default Factory Image 3.4.2. Restoring Board QSPI Flash U4 with Default Factory Image 3.4.3. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Installing Quartus® Prime Software 4.1.2. Setting Up the Programmer 4.1.3. Running the BTS GUI on Windows 4.1.4. Running the BTS GUI on Linux
4.1.4. Running the BTS GUI on Linux x
4.1.4.1. Configuring the Linux UART Environment 4.1.4.2. Launching the BTS
4.3. BTS Functionalities x
4.3.1. Diagnostic GUI 4.3.2. Clock Controller GUI 4.3.3. Power Monitor GUI 4.3.4. MAX® 10 Controller GUI 4.3.5. Agilex™ 5 FPGA Functionality 4.3.6. Information Display 4.3.7. Migrating Development Kit Installer Package from v24.1 to v24.2
4.3.2. Clock Controller GUI x
4.3.2.1. Si5332 Clock 4.3.2.2. Si5518 Clock
4.3.3. Power Monitor GUI x
4.3.3.1. Power Monitor 4.3.3.2. Temperature Monitor
4.3.4. MAX® 10 Controller GUI x
4.3.4.1. Remote I/O Control 4.3.4.2. Expansion Board Control 4.3.4.3. System Control
4.3.4.1. Remote I/O Control x
4.3.4.1.1. Remote Control 4.3.4.1.2. MISC LED Control
4.3.4.1.1. Remote Control x
4.3.4.1.1.1. Push Button 4.3.4.1.1.2. User Switch 4.3.4.1.1.3. MSEL 4.3.4.1.1.4. Si569-1V8
4.3.5. Agilex™ 5 FPGA Functionality x
4.3.5.1. The GPIO Tab 4.3.5.2. The Memory Tab 4.3.5.3. The Transceiver Tab
4.3.5.2. The Memory Tab x
4.3.5.2.1. The DDR4 COMP Tab 4.3.5.2.2. The HPS DDR4 COMP Tab 4.3.5.2.3. The LPDDR4 COMP Tab
4.3.5.3. The Transceiver Tab x
4.3.5.3.1. QSFP Test 4.3.5.3.2. SFP+ Test 4.3.5.3.3. FMC+ Test 4.3.5.3.4. SMA Test
4.3.6. Information Display x
4.3.6.1. Sys Info 4.3.6.2. Connection 4.3.6.3. The Bottom Status Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.3. Configuring the FPGA Device by Avalon® Streaming Modes 5.4. Expansion Boards
5.4. Expansion Boards x
5.4.1. HPS Expansion Board (HPS-EB) 5.4.2. HPS NAND Board (HPS-NB) 5.4.3. HPS Test Board (HPS-TB)
5.4.1. HPS Expansion Board (HPS-EB) x
5.4.1.1. Booting from SD Card using HPS Enablement DC
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Input and Output Components A.7. Memory Interfaces A.8. Communication Interfaces A.9. Expansion Boards A.10. Connectors and Headers
A.2. System Management x
A.2.1. JTAG Master Sources
A.6. Input and Output Components x
A.6.1. Push Buttons A.6.2. Switches A.6.3. LEDs
A.8. Communication Interfaces x
A.8.1. QSFP+ A.8.2. SFP+ A.8.3. Ethernet A.8.4. FMC A.8.5. MIPI A.8.6. USB3.1 A.8.7. HPS IO48 Interface A.8.8. Serial Buses
A.9. Expansion Boards x
A.9.1. HPS Expansion Board (HPS-EB) A.9.2. HPS NAND Board (HPS-NB) A.9.3. HPS Test Board (HPS-TB)
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.8.4. FMC

The Agilex™ 5 FPGA E-Series 065B Premium Development Kit consists of one FMC+ slots that selective support FMC Vita 57.1 for functional expandability. FMC_TX/RX[0:3]_P/N are from transceiver bank 4C and FMC_TX/RX[4:7]_P/N are from bank 4B. All x8 data are terminated to the FMC connector (J34). The low pin count (LPC) LA[0:28] is connected to HSIO bank 3B, and LA[29:30] is connected to HVIO bank 6C through the level translator.

The development kit provides 1.2 V/1.3 V adjustable voltage (VADJ) to FMC for the FMC user defined signals. The development kit does not support FMC cards that are not compliant with Agilex™ 5 FPGA 1.2-V/1.3-V I/O standard.

Table 21.  FMC Connector (J34)
Agilex™ 5 FPGA E-Series 065B Premium Development Kit FMC Connector (J34)
Schematic Signal Name I/O Bank Voltage Level (V) V57.1 Name Pin Number
FMC_GBTCLK0_M2C_P UX 4B — GBTCLK0_M2C_P D4
FMC_GBTCLK0_M2C_N UX 4B — GBTCLK0_M2C_N D5
FMC_GBTCLK1_M2C_P UX 4C — GBTCLK1_M2C_P B20
FMC_GBTCLK1_M2C_N UX 4C — GBTCLK1_M2C_N B21
FMC_RX0_P UX 4B — DP0_M2C_P C6
FMC_RX0_N UX 4B — DP0_M2C_N C7
FMC_RX1_P UX 4B — DP1_M2C_P A2
FMC_RX1_N UX 4B — DP1_M2C_N A3
FMC_RX2_P UX 4B — DP2_M2C_P A6
FMC_RX2_N UX 4B — DP2_M2C_N A7
FMC_RX3_P UX 4B — DP3_M2C_P A10
FMC_RX3_N UX 4B — DP3_M2C_N A11
FMC_RX4_P UX 4C — DP4_M2C_P A14
FMC_RX4_N UX 4C — DP4_M2C_N A15
FMC_RX5_P UX 4C — DP5_M2C_P A18
FMC_RX5_N UX 4C — DP5_M2C_N A19
FMC_RX6_P UX 4C — DP6_M2C_P B16
FMC_RX6_N UX 4C — DP6_M2C_N B17
FMC_RX7_P UX 4C — DP7_M2C_P B12
FMC_RX7_N UX 4C — DP7_M2C_N B13
FMC_TX0_P UX 4B — DP0_C2M_P C2
FMC_TX0_N UX 4B — DP0_C2M_N C3
FMC_TX1_P UX 4B — DP1_C2M_P A22
FMC_TX1_N UX 4B — DP1_C2M_N A23
FMC_TX2_P UX 4B — DP2_C2M_P A26
FMC_TX2_N UX 4B — DP2_C2M_N A27
FMC_TX3_P UX 4B — DP3_C2M_P A30
FMC_TX3_N UX 4B — DP3_C2M_N A31
FMC_TX4_P UX 4C — DP4_C2M_P A34
FMC_TX4_N UX 4C — DP4_C2M_N A35
FMC_TX5_P UX 4C — DP5_C2M_P A38
FMC_TX5_N UX 4C — DP5_C2M_N A39
FMC_TX6_P UX 4C — DP6_C2M_P B36
FMC_TX6_N UX 4C — DP6_C2M_N B37
FMC_TX7_P UX 4C — DP7_C2M_P B32
FMC_TX7_N UX 4C — DP7_C2M_N B33
FMC_1V2_LA_P0 HSIO 3B 1.2 LA00_P_CC G6
FMC_1V2_LA_N0 HSIO 3B 1.2 LA00_N_CC G7
FMC_1V2_LA_P1 HSIO 3B 1.2 LA01_P_CC D8
FMC_1V2_LA_N1 HSIO 3B 1.2 LA01_N_CC D9
FMC_1V2_LA_P2 HSIO 3B 1.2 LA02_P H7
FMC_1V2_LA_N2 HSIO 3B 1.2 LA02_N H8
FMC_1V2_LA_P3 HSIO 3B 1.2 LA03_P G9
FMC_1V2_LA_N3 HSIO 3B 1.2 LA03_N G10
FMC_1V2_LA_P4 HSIO 3B 1.2 LA04_P H10
FMC_1V2_LA_N4 HSIO 3B 1.2 LA04_N H11
FMC_1V2_LA_P5 HSIO 3B 1.2 LA05_P D11
FMC_1V2_LA_N5 HSIO 3B 1.2 LA05_N D12
FMC_1V2_LA_P6 HSIO 3B 1.2 LA06_P C10
FMC_1V2_LA_N6 HSIO 3B 1.2 LA06_N C11
FMC_1V2_LA_P7 HSIO 3B 1.2 LA07_P H13
FMC_1V2_LA_N7 HSIO 3B 1.2 LA07_N H14
FMC_1V2_LA_P8 HSIO 3B 1.2 LA08_P G12
FMC_1V2_LA_N8 HSIO 3B 1.2 LA08_N G13
FMC_1V2_LA_P9 HSIO 3B 1.2 LA09_P D14
FMC_1V2_LA_N9 HSIO 3B 1.2 LA09_N D15
FMC_1V2_LA_P10 HSIO 3B 1.2 LA10_P C14
FMC_1V2_LA_N10 HSIO 3B 1.2 LA10_N C15
FMC_1V2_LA_P11 HSIO 3B 1.2 LA11_P H16
FMC_1V2_LA_N11 HSIO 3B 1.2 LA11_N H17
FMC_1V2_LA_P12 HSIO 3B 1.2 LA12_P G15
FMC_1V2_LA_N12 HSIO 3B 1.2 LA12_N G16
FMC_1V2_LA_P13 HSIO 3B 1.2 LA13_P D17
FMC_1V2_LA_N13 HSIO 3B 1.2 LA13_N D18
FMC_1V2_LA_P14 HSIO 3B 1.2 LA14_P C18
FMC_1V2_LA_N14 HSIO 3B 1.2 LA14_N C19
FMC_1V2_LA_P15 HSIO 3B 1.2 LA15_P H19
FMC_1V2_LA_N15 HSIO 3B 1.2 LA15_N H20
FMC_1V2_LA_P16 HSIO 3B 1.2 LA16_P G18
FMC_1V2_LA_N16 HSIO 3B 1.2 LA16_N G19
FMC_1V2_LA_P17 HSIO 3B 1.2 LA17_P_CC D20
FMC_1V2_LA_N17 HSIO 3B 1.2 LA17_N_CC D21
FMC_1V2_LA_P18 HSIO 3B 1.2 LA18_P_CC C22
FMC_1V2_LA_N18 HSIO 3B 1.2 LA18_N_CC C23
FMC_1V2_LA_P19 HSIO 3B 1.2 LA19_P H22
FMC_1V2_LA_N19 HSIO 3B 1.2 LA19_N H23
FMC_1V2_LA_P20 HSIO 3B 1.2 LA20_P G21
FMC_1V2_LA_N20 HSIO 3B 1.2 LA20_N G22
FMC_1V2_LA_P21 HSIO 3B 1.2 LA21_P H25
FMC_1V2_LA_N21 HSIO 3B 1.2 LA21_N H26
FMC_1V2_LA_P22 HSIO 3B 1.2 LA22_P G24
FMC_1V2_LA_N22 HSIO 3B 1.2 LA22_N G25
FMC_1V2_LA_P23 HSIO 3B 1.2 LA23_P D23
FMC_1V2_LA_N23 HSIO 3B 1.2 LA23_N D24
FMC_1V2_LA_P24 HSIO 3B 1.2 LA24_P H28
FMC_1V2_LA_N24 HSIO 3B 1.2 LA24_N H29
FMC_1V2_LA_P25 HSIO 3B 1.2 LA25_P G27
FMC_1V2_LA_N25 HSIO 3B 1.2 LA25_N G28
FMC_1V2_LA_P26 HVIO 6C 1.2 (converted) LA26_P D26
FMC_1V2_LA_N26 HVIO 6C 1.2 (converted) LA26_N D27
FMC_1V2_LA_P27 HVIO 6C 1.2 (converted) LA27_P C26
FMC_1V2_LA_N27 HVIO 6C 1.2 (converted) LA27_N C27
FMC_1V2_LA_P28 HVIO 6C 1.2 (converted) LA28_P H31
FMC_1V2_LA_N28 HVIO 6C 1.2 (converted) LA28_N H32
FMC_1V2_LA_P29 HVIO 6C 1.2 (converted) LA29_P G30
FMC_1V2_LA_N29 HVIO 6C 1.2 (converted) LA29_N G31
FMC_1V2_LA_P30 HVIO 6C 1.2 (converted) LA30_P H34
FMC_1V2_LA_N30 HVIO 6C 1.2 (converted) LA30_N H35
FMC_1V2_LA_P31 HVIO 6C 1.2 (converted) LA31_P G33
FMC_1V2_LA_N31 HVIO 6C 1.2 (converted) LA31_N G34
FMC_1V2_LA_P32 HVIO 6C 1.2 (converted) LA32_P H37
FMC_1V2_LA_N32 HVIO 6C 1.2 (converted) LA32_N H38
FMC_1V2_LA_P33 HVIO 6C 1.2 (converted) LA33_P G36
FMC_1V2_LA_N33 HVIO 6C 1.2 (converted) LA33_N G37
FMC_CLK0_M2C_P HSIO 3B 1.2 CLK0_M2C_P H4
FMC_CLK0_M2C_N HSIO 3B 1.2 CLK0_M2C_N H5
FMC_CLK1_M2C_P HSIO 3B 1.2 CLK1_M2C_P G2
FMC_CLK1_M2C_N HSIO 3B 1.2 CLK1_M2C_N G3
FMC_CLK2_M2C_P HSIO 3B 1.2 CLK2_M2C_P K4
FMC_CLK2_M2C_N HSIO 3B 1.2 CLK2_M2C_N K5
FMC_CLK3_M2C_P HSIO 3B 1.2 CLK3_M2C_P J2
FMC_CLK3_M2C_N HSIO 3B 1.2 CLK3_M2C_N J3
FMC_REFCLK_C2M_P HSIO 3B 1.2 REFCLK_C2M_P L20
FMC_REFCLK_C2M_N HSIO 3B 1.2 REFCLK_C2M_N L21
FMC_REFCLK_M2C_P HSIO 3B 1.2 REFCLK_M2C_P L24
FMC_REFCLK_M2C_N HSIO 3B 1.2 REFCLK_M2C_N L25
FMC_GA0 — 3.3 GA0 C34
FMC_GA1 — 3.3 GA1 D35
FMC_PG_C2M — 3.3 PG_C2M D1
FMC_PG_M2C — 3.3 PG_M2C F1
FMC_PRSNT_N — 3.3 PRSNT_M2C_L H2
FMC_CLK_DIR — 3.3 CLK_DIR B1
FMC_SCL — 3.3 SCL C30
FMC_SDA — 3.3 SDA C31
FMC_TCK — 3.3 TCK D29
FMC_TDI — 3.3 TDI D30
FMC_TD0 — 3.3 TDO D31
FMC_TMS — 3.3 TMS D33
FMC_TRST_L — 3.3 TRST_L D34
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