Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide

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ID 814550
Date 5/24/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash U4 with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing Quartus® Prime Software 4.1.5. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. Diagnostic GUI 4.3.2. Clock Controller GUI 4.3.3. Power Monitor GUI 4.3.4. MAX® 10 Controller GUI 4.3.5. Agilex™ 5 FPGA E-Series Test Functionality 4.3.6. Information Display
4.3.2. Clock Controller GUI x
4.3.2.1. Si5332 Clock 4.3.2.2. Si5518 Clock
4.3.3. Power Monitor GUI x
4.3.3.1. Power Monitor 4.3.3.2. Temperature Monitor
4.3.4. MAX® 10 Controller GUI x
4.3.4.1. Remote I/O Control 4.3.4.2. Expansion Board Control 4.3.4.3. System Control
4.3.4.1. Remote I/O Control x
4.3.4.1.1. Remote Control 4.3.4.1.2. MISC LED Control
4.3.4.1.1. Remote Control x
4.3.4.1.1.1. Push Button 4.3.4.1.1.2. User Switch 4.3.4.1.1.3. MSEL 4.3.4.1.1.4. Si569-1V8
4.3.5. Agilex™ 5 FPGA E-Series Test Functionality x
4.3.5.1. DDR4 Test 4.3.5.2. HPS DDR4 Test 4.3.5.3. LPDDR4 Test 4.3.5.4. QSFP Test 4.3.5.5. SFP+ Test 4.3.5.6. FMC+ Test 4.3.5.7. SMA Test
4.3.6. Information Display x
4.3.6.1. Sys Info 4.3.6.2. Connection 4.3.6.3. The Bottom Status Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.3. Configuring the FPGA Device by Avalon® Streaming Modes 5.4. Expansion Boards
5.4. Expansion Boards x
5.4.1. HPS Expansion Board (HPS-EB) 5.4.2. HPS NAND Board (HPS-NB) 5.4.3. HPS Test Board (HPS-TB)
6. Custom Projects for the Development Kit x
6.1. Golden Top
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Input and Output Components A.7. Memory Interfaces A.8. Communication Interfaces A.9. Expansion Boards A.10. Connectors and Headers
A.2. System Management x
A.2.1. JTAG Master Sources
A.6. Input and Output Components x
A.6.1. Push Buttons A.6.2. Switches A.6.3. LEDs
A.8. Communication Interfaces x
A.8.1. QSFP+ A.8.2. SFP+ A.8.3. Ethernet A.8.4. FMC A.8.5. MIPI A.8.6. USB3.1 A.8.7. HPS IO48 Interface A.8.8. Serial Buses
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.8.4. FMC

The Agilex™ 5 FPGA E-Series 065B Premium Development Kit consists of one FMC+ slots that selective support FMC Vita 57.1 for functional expandability. FMC_TX/RX[0:3]_P/N are from transceiver bank 4C and FMC_TX/RX[4:7]_P/N are from bank 4B. All x8 data are terminated to the FMC connector (J34). The low pin count (LPC) LA[0:28] is connected to HSIO bank 3B, and LA[29:30] is connected to HVIO bank 6C through the level translator.

The development kit provides 1.2 V/1.3 V adjustable voltage (VADJ) to FMC for the FMC user defined signals. The development kit does not support FMC cards that are not compliant with Agilex™ 5 FPGA 1.2-V/1.3-V I/O standard.

Table 21.  FMC Connector (J34)
Schematic Signal Name Description Remark
FMC_TX[0:7]_P/N Transmit data differential pairs Connect to transceiver bank 4B and 4C
FMC_RX[0:7]_P/N Receive data differential pairs Connect to transceiver bank 4B and 4C
FMC_1V2_LA_P[0:28] User defined signals on LPC Connect to HSIO bank 3B (1.2 V)
FMC_1V2_LA_P[29:33] User defined signals on LPC Connect to HVIO bank 6C (3.3 V) via voltage converter
FMC_CLK[0:3]_M2C_P/N Clock driven from FMC card to FPGA Connect to HSIO bank 3B (1.2 V)
FMC_GBTCLK[0:3]_M2C_P/N Reference clock for differential pair data signals Connect to transceiver bank 4B and 4C
FMC_PG_C2M Power good signal from the development kit Connect to the MAX® 10 controller
FMC_PG_M2C Power good signal from the FMC card Connect to the MAX® 10 controller
FMC_CLK_DIR Clock driven control signal Pull high to 3.3 V
FMC_SCL I2C serial clock Connect to HVIO bank 6C (3.3 V)
FMC_SDA I2C serial data Connect to HVIO bank 6C (3.3 V)
FMC_TCK JTAG clock Connect to the MAX® 10 controller
FMC_TDI JTAG data in Connect to the MAX® 10 controller
FMC_TDO JTAG data out Connect to the MAX® 10 controller
FMC_TMS JTAG mode select Connect to the MAX® 10 controller
FMC_REFCLK_C2M_P/N Optional Refclk driven from the FPGA to the FMC card for synchronization Connect to HSIO bank 3B (1.2 V)
FMC_REFCLK_M2C_P/N Optional Refclk driven from the FMC card to the FPGA for synchronization Connect to HSIO bank 3B (1.2 V)
FMC_PRSNT_N FMC card present signal Connect to the MAX® 10 controller and HVIO bank 6C (3.3 V)
Level Two Title