Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide

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ID 814550
Date 5/24/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash U4 with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing Quartus® Prime Software 4.1.5. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. Diagnostic GUI 4.3.2. Clock Controller GUI 4.3.3. Power Monitor GUI 4.3.4. MAX® 10 Controller GUI 4.3.5. Agilex™ 5 FPGA E-Series Test Functionality 4.3.6. Information Display
4.3.2. Clock Controller GUI x
4.3.2.1. Si5332 Clock 4.3.2.2. Si5518 Clock
4.3.3. Power Monitor GUI x
4.3.3.1. Power Monitor 4.3.3.2. Temperature Monitor
4.3.4. MAX® 10 Controller GUI x
4.3.4.1. Remote I/O Control 4.3.4.2. Expansion Board Control 4.3.4.3. System Control
4.3.4.1. Remote I/O Control x
4.3.4.1.1. Remote Control 4.3.4.1.2. MISC LED Control
4.3.4.1.1. Remote Control x
4.3.4.1.1.1. Push Button 4.3.4.1.1.2. User Switch 4.3.4.1.1.3. MSEL 4.3.4.1.1.4. Si569-1V8
4.3.5. Agilex™ 5 FPGA E-Series Test Functionality x
4.3.5.1. DDR4 Test 4.3.5.2. HPS DDR4 Test 4.3.5.3. LPDDR4 Test 4.3.5.4. QSFP Test 4.3.5.5. SFP+ Test 4.3.5.6. FMC+ Test 4.3.5.7. SMA Test
4.3.6. Information Display x
4.3.6.1. Sys Info 4.3.6.2. Connection 4.3.6.3. The Bottom Status Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.3. Configuring the FPGA Device by Avalon® Streaming Modes 5.4. Expansion Boards
5.4. Expansion Boards x
5.4.1. HPS Expansion Board (HPS-EB) 5.4.2. HPS NAND Board (HPS-NB) 5.4.3. HPS Test Board (HPS-TB)
6. Custom Projects for the Development Kit x
6.1. Golden Top
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Input and Output Components A.7. Memory Interfaces A.8. Communication Interfaces A.9. Expansion Boards A.10. Connectors and Headers
A.2. System Management x
A.2.1. JTAG Master Sources
A.6. Input and Output Components x
A.6.1. Push Buttons A.6.2. Switches A.6.3. LEDs
A.8. Communication Interfaces x
A.8.1. QSFP+ A.8.2. SFP+ A.8.3. Ethernet A.8.4. FMC A.8.5. MIPI A.8.6. USB3.1 A.8.7. HPS IO48 Interface A.8.8. Serial Buses
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.5. General Input/Output

Table 9.   MAX® 10
Schematic Signal Name Description
MAX10_SI5518A_GPIO0 Interrupt pin status output for SI5518A or chip select of secondary SPI port.
MAX10_SI5518A_GPIO1 Loss of lock status output for DSPLL A or SDIO of secondary SPI port.
MAX10_SI5518A_GPIO2 Output enable control pin or SCLK of secondary SPI port.
MAX10_SI5518A_GPIO3 Reserve GPIO for SI5518A.
SI5518A_GPIO_SEL

Control pin for SI5518A GPIOs source.

  • High: MAX10 controls SI5518A GPIOs
  • Low: FPGA controls SI5518A GPIOs
SI5332A_1_IN1 Clock in SEL0 for SI5332A (U411).
SI5332A_1_IN2 Clock in SEL1 for SI5332A (U411).
SI5332A_1_IN3 Spread spectrum enable for SI5332A (U411).
SI5332A_1_IN4 Output enable pin for SI5332A (U411).
SI5332A_1_IN5

Output frequency select pin for SI5332A (U411) OUT2.

  • High: 199.95 MHz
  • Low: 116.625 MHz
SI5332A_2_IN1 Clock in SEL0 for SI5332A (U412).
SI5332A_2_IN2 Clock in SEL1 for SI5332A (U412).
SI5332A_2_IN3 Reserved for SI5332A (U412).
SI5332A_2_IN4 Reserved for SI5332A (U412).
SI5332A_2_IN5 Reserved for SI5332A (U412).
MAX_FPGA_SPARE0 Reserved GPIO between MAX® 10 and Agilex™ 5 FPGA.
MAX_FPGA_SPARE1 Reserved GPIO between MAX® 10 and Agilex™ 5 FPGA.
MAX_FPGA_SPARE2 Reserved GPIO between MAX® 10 and Agilex™ 5 FPGA.
MAX_FPGA_SPARE3 Reserved GPIO between MAX® 10 and Agilex™ 5 FPGA.
MAX_FPGA_SPARE4 Reserved GPIO between MAX® 10 and Agilex™ 5 FPGA.
MAX_FPGA_SPARE5 Reserved GPIO between MAX® 10 and Agilex™ 5 FPGA.
MAX_FPGA_SPARE6 Reserved GPIO between MAX® 10 and Agilex™ 5 FPGA.
MAX_FPGA_SPARE7 Reserved GPIO between MAX® 10 and Agilex™ 5 FPGA.
Table 10.   Agilex™ 5 FPGA
Schematic Signal Name Description
FPGA_USER_IO1 GPIO pin for FPGA HVIO bank.
FPGA_USER_IO2 GPIO pin for FPGA HVIO bank.
FPGA_USER_IO3 GPIO pin for FPGA HVIO bank.
FPGA_USER_IO4 GPIO pin for FPGA HVIO bank.
FPGA_USER_IO5 GPIO pin for FPGA HVIO bank.
FPGA_USER_IO6 GPIO pin for FPGA HVIO bank.
FPGA_USER_IO7 GPIO pin for FPGA HVIO bank.
FPGA_USER_IO8 GPIO pin for FPGA HVIO bank.
HSIO_IO1 GPIO pin for FPGA HSIO bank.
HSIO_IO2 GPIO pin for FPGA HSIO bank.
HSIO_IO3 GPIO pin for FPGA HSIO bank.
HSIO_IO4 GPIO pin for FPGA HSIO bank.
FPGA_USER_LED1_1V1 Output for LED1.
FPGA_USER_LED2_1V1 Output for LED2.
FPGA_USER_LED3_1V1 Output for LED3.
FPGA_USER_LED4_1V1 Output for LED4.
FPGA_1V1_SI5518A_GPIO0 Interrupt pin status output for SI5518A or chip select of secondary SPI port.
FPGA_1V1_SI5518A_GPIO1 Loss of lock status output for DSPLL A or SDIO of secondary SPI port.
FPGA_1V1_SI5518A_GPIO2 Output enable control pin or SCLK of secondary SPI port.
FPGA_1V1_SI5518A_GPIO3 Reserve GPIO for SI5518A.
FMC_MIPI_CLK_SEL

Control pin for U377 clock in source.

  • High: MIPI_REFCLK as clock out
  • Low: FMC_CLK2_M2C as clock out
5518_5332_SEL_1V8

Control pin for U419 clock in source.

  • High: QSFP1_REFCLK (from SI5518) as clock out
  • Low: SFP_REFCLK (form SI5332) as clock out
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