Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide

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ID 814550
Date 8/05/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Installing the HPS Expansion Board (HPS-EB) 3.2. Default Settings 3.3. Powering Up the Development Kit 3.4. Performing Board Restore
3.4. Performing Board Restore x
3.4.1. Restoring Board QSPI Flash U10 with Default Factory Image 3.4.2. Restoring Board QSPI Flash U4 with Default Factory Image 3.4.3. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Installing Quartus® Prime Software 4.1.2. Setting Up the Programmer 4.1.3. Running the BTS GUI on Windows 4.1.4. Running the BTS GUI on Linux
4.1.4. Running the BTS GUI on Linux x
4.1.4.1. Configuring the Linux UART Environment 4.1.4.2. Launching the BTS
4.3. BTS Functionalities x
4.3.1. Diagnostic GUI 4.3.2. Clock Controller GUI 4.3.3. Power Monitor GUI 4.3.4. MAX® 10 Controller GUI 4.3.5. Agilex™ 5 FPGA Functionality 4.3.6. Information Display 4.3.7. Migrating Development Kit Installer Package from v24.1 to v24.2
4.3.2. Clock Controller GUI x
4.3.2.1. Si5332 Clock 4.3.2.2. Si5518 Clock
4.3.3. Power Monitor GUI x
4.3.3.1. Power Monitor 4.3.3.2. Temperature Monitor
4.3.4. MAX® 10 Controller GUI x
4.3.4.1. Remote I/O Control 4.3.4.2. Expansion Board Control 4.3.4.3. System Control
4.3.4.1. Remote I/O Control x
4.3.4.1.1. Remote Control 4.3.4.1.2. MISC LED Control
4.3.4.1.1. Remote Control x
4.3.4.1.1.1. Push Button 4.3.4.1.1.2. User Switch 4.3.4.1.1.3. MSEL 4.3.4.1.1.4. Si569-1V8
4.3.5. Agilex™ 5 FPGA Functionality x
4.3.5.1. The GPIO Tab 4.3.5.2. The Memory Tab 4.3.5.3. The Transceiver Tab
4.3.5.2. The Memory Tab x
4.3.5.2.1. The DDR4 COMP Tab 4.3.5.2.2. The HPS DDR4 COMP Tab 4.3.5.2.3. The LPDDR4 COMP Tab
4.3.5.3. The Transceiver Tab x
4.3.5.3.1. QSFP Test 4.3.5.3.2. SFP+ Test 4.3.5.3.3. FMC+ Test 4.3.5.3.4. SMA Test
4.3.6. Information Display x
4.3.6.1. Sys Info 4.3.6.2. Connection 4.3.6.3. The Bottom Status Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.3. Configuring the FPGA Device by Avalon® Streaming Modes 5.4. Expansion Boards
5.4. Expansion Boards x
5.4.1. HPS Expansion Board (HPS-EB) 5.4.2. HPS NAND Board (HPS-NB) 5.4.3. HPS Test Board (HPS-TB)
5.4.1. HPS Expansion Board (HPS-EB) x
5.4.1.1. Booting from SD Card using HPS Enablement DC
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Input and Output Components A.7. Memory Interfaces A.8. Communication Interfaces A.9. Expansion Boards A.10. Connectors and Headers
A.2. System Management x
A.2.1. JTAG Master Sources
A.6. Input and Output Components x
A.6.1. Push Buttons A.6.2. Switches A.6.3. LEDs
A.8. Communication Interfaces x
A.8.1. QSFP+ A.8.2. SFP+ A.8.3. Ethernet A.8.4. FMC A.8.5. MIPI A.8.6. USB3.1 A.8.7. HPS IO48 Interface A.8.8. Serial Buses
A.9. Expansion Boards x
A.9.1. HPS Expansion Board (HPS-EB) A.9.2. HPS NAND Board (HPS-NB) A.9.3. HPS Test Board (HPS-TB)
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide
A. Development Kit Components
B. Additional Information

1.2. Feature Summary

  • Agilex™ 5 FPGA E-Series 065B device (group B) in 1591 ball anywhere BGA package
    • Monolithic die architecture
    • One dual-core 64-bit Arm* Cortex* -A76 and one dual-core 64-bit Arm* Cortex* -A55 hard processor system (HPS)
    • Fixed core voltage
    • 24 transceiver channels support 10 GbE hard IP (MAC, PCS, and FEC) with IEEE 1588/up to 17.16 Gbps NRZ/up to PCIe* 4 x4 hard IP
      Note: The ES development kit is installed with –6s speed grade FPGA and only supports up to PCIe* Gen 3.0.
    • 656 K logic elements (LE)
    • 222 K adaptive logic modules (ALM)
    • 846 digital signal processing (DSP) blocks
  • FPGA configuration
    • Avalon® streaming interface x8 and Active Serial (AS) x4 configuration mode support
    • 2 Gb flash for Avalon® streaming interface x8 configuration mode
    • 2 Gb flash for AS x4 configuration mode
    • Built-in Intel® FPGA Download Cable II for JTAG mode device programming
  • Programmable clock sources
  • Transceiver interfaces
    • 2x QSFP+ (4x 10G) optical module interface connected to UX 1A and 1B
    • 1x SGMII (2.5G) via RJ45 and 1x USB 3.1 (5G) via HPS card connected to UX 1C
    • 2x SFP+ (1x 10G) optical module interface and 2x SMA (17G) connected to UX 4A
    • 1x PCIe* Gen4 x4 root port via FMC connector connected to UX 4B and 4C
      Note: The ES development kit is installed with –6s speed grade FPGA and only supports up to PCIe* Gen 3.0.
  • Other interfaces
    • IO48 interface for HPS Expansion Board via ADM connector
    • 4 channel MIPI interface to high-speed I/Os (HSIO) bank via 22 pins FPC connector
    • FMC interface via FMC+ connector (selective VITA 57.4 support)
  • Memory interfaces
    • 1x 8 GB DDR4-1600 (x32 with ECC) for fabric I/O memory
    • 1x 8 GB DDR4-1600 (x32 with ECC) for HPS processor memory
    • 1x 4 GB LPDDR4-1600 x32 for fabric I/O memory
  • Communication ports
    • JTAG header
    • Micro USB onboard Intel® FPGA Download Cable II
  • Buttons, switches, and LEDs
    • HPS reset push button
    • Four dedicated user push buttons
    • Four dedicated user DIP switches
    • Four dedicated user LEDs
    • Board power good LED
    • MAX® 10 configuration done LED
    • FPGA configuration done LED
  • Heatsink and fan
    • Air-cooled heatsink assembly for FPGA
    • Red over-temperature warning LED
  • Power
    • PCIe* input power including required 2x4 auxiliary power connector
    • Green power-good status LED
    • On/Off slide power switch for benchtop operation
    • Onboard power and temperature measurement circuitry
  • Mechanical
    • 7.6" x 10.2" board size
  • Operating environment
    • Maximum ambient temperature of 0⁰C–35⁰C
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