Visible to Intel only — GUID: lbn1673393411801
Ixiasoft
Visible to Intel only — GUID: lbn1673393411801
Ixiasoft
5.1. Ethernet Media Access Controller
The hard processor system (HPS) provides three Ethernet media access controller (EMAC) peripherals. The EMACs are based on Synopsys* Ethernet XGMAC IP (version 3.10a). Each EMAC can be used to transmit and receive data at 10M/100M/1G/2.5G over Ethernet connections in compliance with the IEEE 802.3-2018 specification and enables support for Time Sensitive Networking (TSN) applications.
The EMAC has an extensive memory-mapped control and status register (CSR) set, which can be accessed by the Arm* processors. For an understanding of this chapter, you should be familiar with the basics of IEEE 802.3 media access control (MAC).
Section Content
EMAC Differences Among Intel SoC Device Families
EMAC Use Cases
EMAC Features
EMAC System Integration
EMAC Signal Description and Interfaces
EMAC Functional Description
EMAC Programming Model
EMAC Address Map and Register Definitions
EMAC Design Guidelines and Examples