Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.1. Ethernet Media Access Controller

The hard processor system (HPS) provides three Ethernet media access controller (EMAC) peripherals. The EMACs are based on Synopsys* Ethernet XGMAC IP (version 3.10a). Each EMAC can be used to transmit and receive data at 10M/100M/1G/2.5G over Ethernet connections in compliance with the IEEE 802.3-2018 specification and enables support for Time Sensitive Networking (TSN) applications.

The EMAC has an extensive memory-mapped control and status register (CSR) set, which can be accessed by the Arm* processors. For an understanding of this chapter, you should be familiar with the basics of IEEE 802.3 media access control (MAC).