Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs
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Visible to Intel only — GUID: yfx1683641167159
Ixiasoft
15.5.1.4.1. Debug Reset Request via Reset Manager CSR
Internal software performs a memory-mapped register access to request the debug subsystem reset. Refer to the Reset Manager register descriptions for more details of the register bits described in this section.
- Make a debug reset request by sending a request to the DBGMODRST register in the reset manager. Setting the dbg_rst bit triggers the debug reset state machine to initiate a debug reset sequence.
- Check the status of a debug reset request by accessing the DBGRSTCMPLT status register in the reset manager.
- The swdbgrstcmplt bit is set when the debug reset sequence has been completed.
- The swdbgrstcmplt bit is cleared by hardware when the software removes the debug reset request by negating the dbg_rst bit.