Visible to Intel only — GUID: mbs1673393412577
Ixiasoft
Visible to Intel only — GUID: mbs1673393412577
Ixiasoft
5.1.1. EMAC Differences Among Intel SoC Device Families
EMAC Feature |
Cyclone® V SoC, Arria® V SoC |
Arria® 10 SoC | Stratix® 10 SoC, Intel® Agilex™ 7 F-Series/I-Series/ M-Series SoC |
Agilex™ 5 E-Series/D-Series SoC |
---|---|---|---|---|
Synopsys IP version |
GMAC 3.70a |
GMAC 3.72a |
GMAC 3.73a |
XGMAC 3.10a |
Number of EMACs supported |
2 |
3 |
3 |
3 |
Reduced Media Independent Interface (RMII) for 10/100 |
No |
Yes |
Yes |
No |
Reduced Gigabit Media Independent Interface (RGMII) |
Yes |
Yes |
Yes |
Yes |
Gigabit Media Independent Interface (GMII) to FPGA fabric |
Yes |
Yes |
Yes |
Yes 13 |
GMII adaptation to RMII14 | Yes | Yes | Yes | No |
GMII adaptation to RGMII | Yes | Yes | No | Yes |
GMII adaptation to SGMII | Yes | Yes | Yes | Yes |
GMII adaptation to SGMII+ | No | No | No | Yes |
Enable TSN support |
No |
No |
No |
Yes |
Serial timestamp interface |
Yes |
Yes |
Yes |
Yes |
Synchronized Multidrop Timestamp Gathering (SMTG) IP support |
No |
No |
No |
Yes |
ECC protection for internal memory |
Included |
Enhanced |
Enhanced |
Enhanced |
ECC errors can be directly injected from the ECC controller |
N/A |
Yes |
Yes |
Yes |
FIFO size |
RX: 4 KB TX: 4 KB |
RX: 16 KB TX: 4 KB |
RX: 16 KB TX: 16 KB |
RX: 16 KB TX: 32 KB |
HPS PHY interface I/O bank location |
HPS I/O |
HPS shared I/O bank |
HPS dedicated I/O bank |
HPS dedicated I/O bank |
HPS I/O PHY RGMII-ID support |
No |
Facilitated with delay elements in I/O element |
Enhanced support with delay elements in pin MUX15 |
Enhanced support with delay elements in pin MUX 15 |