Visible to Intel only — GUID: fru1704161746911
Ixiasoft
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. GTS Transceivers Signals
6.4. GTS Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. Miscellaneous Status and Debug Signals
6.7. Reset Signals
6.8. Clocks
6.9. Flow Control Interface
6.10. GTS Reset Sequencer Intel® FPGA IP
Visible to Intel only — GUID: fru1704161746911
Ixiasoft
3.6.1. Pin Assignments
When you integrate your Low Latency 40G Ethernet Intel® FPGA IP instance in your Agilex™ 5 design, you must make appropriate pin assignments. While compiling the IP alone, you can create virtual pins to avoid making specific pin assignments for top-level signals. When you are ready to map the design to hardware, you can change to the correct pin assignments.
Related Information