Power Management User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813161
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Power Management Overview 2. Agilex™ 5 Power Basics 3. Agilex™ 5 Power and I/O State Sequencing 4. Agilex™ 5 Sensor Monitoring System 5. Agilex™ 5 Power Optimization Techniques and Features 6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Agilex™ 5 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Power and Thermal Calculator 2.4. Power Analyzer
3. Agilex™ 5 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Floating Voltage 3.4. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in HSIO, HVIO, HPS IO, and SDM IO Banks During Power Sequencing
3.4. Power-On Reset x
3.4.1. Power Supplies Monitored by the POR Circuitry
4. Agilex™ 5 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function 4.1.2. Voltage Sensor Voltage Reference Pins
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Guidelines: Connecting External Reference to the Agilex™ 5 Voltage Reference Pins 4.3.3. Temperature Monitor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 5 Remote TSD
5. Agilex™ 5 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Agilex™ 5 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Agilex™ 5 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Agilex™ 5 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Agilex™ 5 Power Management Overview
2. Agilex™ 5 Power Basics
3. Agilex™ 5 Power and I/O State Sequencing
4. Agilex™ 5 Sensor Monitoring System
5. Agilex™ 5 Power Optimization Techniques and Features
6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs

4.2.3. Temperature Sensor Locations

The Agilex™ 5 local and remote TSDs are located in the core fabric and GTS transceiver banks. There are several local temperature sensor locations within the core fabric to support temperature readout across the core fabric and the GTS transceiver banks.
Figure 8. Temperature Sensing Diode LocationsThis figure shows approximate locations of the temperature sensors and is not to scale. The figure shows the view of the die as shown in the Quartus® Prime Chip Planner. In the Pin Planner, this corresponds to the "Bottom View".


Note: The count and availability of the temperature sensors, TSDs, and GTS transceiver banks vary among Agilex™ 5 devices. The HPS bank is available only in Agilex™ 5 SoC FPGAs.
  • To monitor the HPS temperature, use TSD 5 in location 4.
  • To monitor the SDM temperature, use the TSD in location 0.
Figure 9. Bit Format to Mailbox Client with Avalon® Streaming Interface IP to Specify Local TSDs to ReadTo specify which local TSD to read, provide the Mailbox Client with Avalon® Streaming Interface IP with the 32-bit value in fixed length hexadecimal codes.
Table 7.  Local Temperature Sensor Locations and Corresponding Bank NamesThe availability of the sensor locations and TSDs varies among Agilex™ 5 FPGAs. This table lists the availability of temperature sensor resources for E-Series devices.
Sensor Location TSD Location D-Series Devices E-Series Devices

A5D 010

A5D 025

A5D 031

A5D 051

A5D 064

A5E 005B

A5E 007B

A5E 008B

A5E 013A

A5E 013B

 A5E 028A

A5E 028B

A5E 043A

A5E 052A

A5E 065A

A5E 043B

A5E 052B

A5E 065B
0 1 Yes Yes Yes Yes Yes Yes
1 2 Yes Yes — — Yes Yes
3 Yes Yes — Yes Yes Yes
4 Yes Yes — Yes Yes Yes
3 1 — — Yes Yes — —
2 Yes Yes — — — Yes
3 Yes Yes — — Yes Yes
4 1 — — Yes — — —
2 — Yes — — — —
3 — Yes — — — Yes
4 Yes Yes — Yes Yes Yes
5 Yes Yes — Yes Yes Yes
Table 8.  Local Temperature Sensor Locations and Equivalent Remote TSD Pin NamesNot all locations have a remote TSD. In locations with a remote TSD, the remote TSD is physically located next to the local TSDs that are marked as local TSD 1. The temperature sensor locations of the core fabric and GTS transceiver banks are as shown in the preceding figure.
Location Number

Sensor Location

[31..16]

(Hexadecimal code)

Supported Channel 4

(Specify sensor bitmask[15..0] as hexadecimal value)

Equivalent Remote TSD Pin Name

(Next to local TSD 1 in sensor location)
0 0000 0 5 TEMPDIODE0Ap / TEMPDIODE0An
1 0001 4, 3, 2, 0 —
3 0003 3, 2, 1, 0 —
4 0004 5, 4, 3, 2, 1, 0 —
Related Information
4 For sensor locations with several local TSDs, channel 0 (mask [0]) returns the highest temperature among the local TSDs in the particular location. For sensor locations with one local TSD, channel 0 returns the same value as channel 1.
5 For location 0, only channel 0 (mask [0]) is supported, returning the temperature reading for the TSD in that location.
Level Two Title