Power Management User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813161
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Power Management Overview 2. Agilex™ 5 Power Basics 3. Agilex™ 5 Power and I/O State Sequencing 4. Agilex™ 5 Sensor Monitoring System 5. Agilex™ 5 Power Optimization Techniques and Features 6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Agilex™ 5 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Intel® FPGA Power and Thermal Calculator 2.4. Power Analyzer
3. Agilex™ 5 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Floating Voltage 3.4. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in HSIO, HVIO, HPS IO, and SDM IO Banks During Power Sequencing
3.4. Power-On Reset x
3.4.1. Power Supplies Monitored by the POR Circuitry
4. Agilex™ 5 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function 4.1.2. Voltage Sensor Voltage Reference Pins
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Guidelines: Connecting External Reference to the Agilex™ 5 Voltage Reference Pins 4.3.3. Temperature Monitor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 5 Remote TSD
5. Agilex™ 5 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Agilex™ 5 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Agilex™ 5 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Agilex™ 5 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Agilex™ 5 Power Management Overview
2. Agilex™ 5 Power Basics
3. Agilex™ 5 Power and I/O State Sequencing
4. Agilex™ 5 Sensor Monitoring System
5. Agilex™ 5 Power Optimization Techniques and Features
6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs

5.1. SmartVID Standard Power Devices

The SmartVID feature compensates for process variation by narrowing the process distribution using voltage adaptation.

This feature is supported in all Agilex™ 5 devices with the –V and –E power options only. For the –V and –E power option devices, you must connect the PWRMGT_SCL and PWRMGT_SDA pins in both the Power Management BUS (PMBus™) master and PMBus slave modes. The PWRMGT_ALERT pin is mandatory for the Agilex™ 5 device in the PMBus slave mode. The PWRMGT_ALERT pin is an active low pin and is used to perform the handshake flow between the FPGA device and an external PMBus master. All connections must be set up on the circuit board and in the Quartus® Prime software.

Table 12.  The PMBus Master and Slave Mode Interfaces for the Agilex™ 5 Devices
PMBus Interfaces Operating Modes
PMBus Master Mode PMBus Slave Mode
PWRMGT_SCL Required Required
PWRMGT_SDA Required Required
PWRMGT_ALERT — Required

The PMBus master and PMBus slave modes only support the 1.8-V single-ended I/O standard.

Note: The PWRMGT_SDA, PWRMGT_SCL, and PWRMGT_ALERT signals are in the undetermined state during device power-up and power-down. The PWRMGT_SDA, PWRMGT_SCL, and PWRMGT_ALERT signals are only valid after the device is fully powered up.

For more information about how to connect these pins on the circuit board, refer to the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs .

For instructions on how to set up the connections in the Quartus® Prime software, refer to the Specifying Power Management and VID Parameters and Options.

Note: Agilex™ 5 standard power devices (–1V, –2V, –2E, and –3V power grades) are SmartVID devices. The core voltage supplies (VCC and VCCP) for each SmartVID device is mandatory to be driven by a PMBus-compliant voltage regulator dedicated to the Agilex™ 5 –V and –E power option devices that is connected to that Agilex™ 5 device via PMBus. Agilex™ 5 devices does not configure or function correctly if the core voltage is driven by a non-PMBus compliant regulator with a fixed output voltage.

Altera programs the optimum voltage level required by each individual Agilex™ 5 device into a fuse block during device manufacturing. The Secure Device Manager (SDM) Power Manager reads these values and can communicate them to an external power regulator or a system power controller through the PMBus interface.

The SmartVID feature allows a power regulator to provide the Agilex™ 5 device with VCC and VCCP voltage levels that maintain the performance of the specific device speed grade. When the SmartVID feature is used:

  1. Agilex™ 5 devices are powered up at 0.80 V for all speed grade devices for both VCC and VCCP .
  2. After the VID-fused value in the Agilex™ 5 device is determined and propagated to the external voltage regulator, both the VCC and VCCP voltages are regulated based on the boosted or amplified VID-fused value.
  3. For a list of fully validated and API validated recommended voltage regulators, refer to the related information.

Section Content
SmartVID Feature Implementation in Agilex 5 Devices
SDM Power Manager
Temperature Compensation
Agilex 5 Power Management and VID Implementation Guide

Related Information
Level Two Title