Power Management User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813161
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Power Management Overview 2. Agilex™ 5 Power Basics 3. Agilex™ 5 Power and I/O State Sequencing 4. Agilex™ 5 Sensor Monitoring System 5. Agilex™ 5 Power Optimization Techniques and Features 6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Agilex™ 5 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Intel® FPGA Power and Thermal Calculator 2.4. Power Analyzer
3. Agilex™ 5 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Floating Voltage 3.4. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in HSIO, HVIO, HPS IO, and SDM IO Banks During Power Sequencing
3.4. Power-On Reset x
3.4.1. Power Supplies Monitored by the POR Circuitry
4. Agilex™ 5 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function 4.1.2. Voltage Sensor Voltage Reference Pins
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Guidelines: Connecting External Reference to the Agilex™ 5 Voltage Reference Pins 4.3.3. Temperature Monitor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 5 Remote TSD
5. Agilex™ 5 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Agilex™ 5 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Agilex™ 5 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode Multi-Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Agilex™ 5 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Agilex™ 5 Power Management Overview
2. Agilex™ 5 Power Basics
3. Agilex™ 5 Power and I/O State Sequencing
4. Agilex™ 5 Sensor Monitoring System
5. Agilex™ 5 Power Optimization Techniques and Features
6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs

5.1.2.1. PMBus Master Mode

In the PMBus master mode, during the initial stage, the SDM Power Manager sets the external voltage regulator to supply VCC and VCCP voltage levels based on the VID-fused value and the device temperature before it starts to configure the FPGA.

After entering user mode (in the monitor stage), the SDM Power Manager monitors temperature changes and decides if the VCC and VCCP output voltage values need to be updated. If voltages require updating, the SDM Power Manager identifies the voltage value based on the fuse values and the current temperature and sends the desired voltage value to the voltage regulators through the PMBus interface.

Figure 12. PMBus Master Mode
Table 15.  Supported Commands for the PMBus Master Mode
Command Name Command Code PMBus Transaction Type Number of Bytes
PAGE 8 00h Write byte 1
VOUT_MODE 20h Read byte 1
VOUT_COMMAND 21h Write word 2
READ_VOUT 8Bh Read word 2
MFR_ADC_CONTROL 9 D8h Write byte 1
STATUS_BYTE 78h Read byte 1
CLEAR_FAULTS 03h Write byte 0
STATUS_WORD 79h Read word 2
Figure 13. Flow between the PMBus Voltage Regulator and FPGA in the PMBus Master Mode

Multi-Master Mode

The PMBus master mode supports the multi-master mode. However, the only supported communication is between the PMBus voltage regulator and a single master at a time.

When multiple devices start to communicate at the same time, the device writing the most zeros to the bus or the slowest device wins the arbitration. The other devices immediately discontinue any operation on the bus. When there is an on-going bus communication, all devices must detect the communication and not interrupt it. The devices must wait for a stop condition to appear before starting communication to the bus. Once the stop condition is received on the bus, the next device that wins arbitration sends a start condition by pulling the PWRMGT_SDA low to re-initialize the bus communication.

In this mode, all master devices must be multi masters in a multi-master system. Single-master systems may not understand the arbitration and the busy detection mechanisms can cause unpredictable results.

8 This is an optional command. This command is only applicable if you enable the PAGE command parameter. For more information, refer to the Power Management and VID Parameters section.
9 This command is sent when you set the device type to LTM4677 only.
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