Power Management User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813161
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Power Management Overview 2. Agilex™ 5 Power Basics 3. Agilex™ 5 Power and I/O State Sequencing 4. Agilex™ 5 Sensor Monitoring System 5. Agilex™ 5 Power Optimization Techniques and Features 6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Agilex™ 5 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Intel® FPGA Power and Thermal Calculator 2.4. Power Analyzer
3. Agilex™ 5 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Floating Voltage 3.4. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in HSIO, HVIO, HPS IO, and SDM IO Banks During Power Sequencing
3.4. Power-On Reset x
3.4.1. Power Supplies Monitored by the POR Circuitry
4. Agilex™ 5 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function 4.1.2. Voltage Sensor Voltage Reference Pins
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Guidelines: Connecting External Reference to the Agilex™ 5 Voltage Reference Pins 4.3.3. Temperature Monitor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 5 Remote TSD
5. Agilex™ 5 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Agilex™ 5 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Agilex™ 5 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Agilex™ 5 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Agilex™ 5 Power Management Overview
2. Agilex™ 5 Power Basics
3. Agilex™ 5 Power and I/O State Sequencing
4. Agilex™ 5 Sensor Monitoring System
5. Agilex™ 5 Power Optimization Techniques and Features
6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs

3.2. Power-Up Sequence Requirements

The power rails in the Agilex™ 5 devices are divided into three groups.

The following figure shows the voltage groups of the Agilex™ 5 devices and their required power-up sequence.

Figure 2. Power-Up Sequence for the Agilex™ 5 Devices
Note: VCCBAT is not in any of the groups in the following table. VCCBAT is a battery supply and is always on. Alternatively, VCCBAT can be tied to VCCR or GND if the battery-backed RAM (BBRAM) is not used for security feature. This is because VCCBAT holds the content of the security keys.

For more information about the VCCBAT connection guidelines and power supply sharing guidelines, refer to the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs .

Table 3.   Agilex™ 5 Voltage Rails Group
Power Group FPGA Core and Hard Processor System (HPS)
Group 1

VCC

VCCP

VCCL_ADC_SDM

VCC_IO_SDM

VCCL_SDM

VCCH_SDM

VCCPLLDIG_SDM

VCCL_HPS

VCCL_HPS_CORE0_CORE1

VCCL_HPS_CORE2

VCCL_HPS_CORE3

VCCPLLDIG1_HPS

VCCPLLDIG2_HPS

VCC_HSSI_[L1,R4]

VCCERT_GTS[L1,R4][A,B,C,D]

Group 2A

VCCPT_HVIO

VCCFUSEWR_SDM

VCCIO_SDM

VCCIO_HPS

VCCPT

VCCPLL_SDM

VCCADC

VCCPLL1_HPS

VCCPLL2_HPS

VCCEHT_GTS[L1,R4][A,B,C,D]

Group 2B

VCCIO_PIO

VCCIO_HVIO

VCCIO_PIO_SDM

VCCRCORE

All power rails in Group 1 must ramp up (in any order) to a minimum of 90% of their respective nominal voltage before the power rails from Group 2A can start ramping up. The power rails within Group 2A can ramp up in any order after the last power rail in Group 1 ramps to the minimum threshold of 90% of its nominal voltage. All power rails in Group 2A must ramp to a minimum threshold of 90% of their nominal value before the Group 2B power rails can start ramping up. The power rails within Group 2B can ramp up in any order after the last power rail in Group 2A ramps up to a minimum threshold of 90% of their full value. For more information, refer to the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs .

All power rails must ramp up monotonically. The power-up sequence must meet the POR delay time. For the POR specifications of the Agilex™ 5 devices, refer to the POR Specifications section in the Agilex™ 5 FPGAs and SoCs Device Data Sheet .

For configuration via protocol (CvP), the total tRAMP must be less than 10 ms from the first power supply ramp-up to the last power supply ramp-up. For the tRAMP specifications, refer to the Recommended Operating Conditions section in the Agilex™ 5 FPGAs and SoCs Device Data Sheet .

For Agilex™ 5 devices, Altera recommends that you reverse the power-up sequence when you power down your device.


Section Content
Guidelines for I/O Pins in HSIO, HVIO, HPS IO, and SDM IO Banks During Power Sequencing

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