Power Management User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813161
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Power Management Overview 2. Agilex™ 5 Power Basics 3. Agilex™ 5 Power and I/O State Sequencing 4. Agilex™ 5 Sensor Monitoring System 5. Agilex™ 5 Power Optimization Techniques and Features 6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Agilex™ 5 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Intel® FPGA Power and Thermal Calculator 2.4. Power Analyzer
3. Agilex™ 5 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Floating Voltage 3.4. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in HSIO, HVIO, HPS IO, and SDM IO Banks During Power Sequencing
3.4. Power-On Reset x
3.4.1. Power Supplies Monitored by the POR Circuitry
4. Agilex™ 5 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function 4.1.2. Voltage Sensor Voltage Reference Pins
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Guidelines: Connecting External Reference to the Agilex™ 5 Voltage Reference Pins 4.3.3. Temperature Monitor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 5 Remote TSD
5. Agilex™ 5 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Agilex™ 5 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Agilex™ 5 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Agilex™ 5 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Agilex™ 5 Power Management Overview
2. Agilex™ 5 Power Basics
3. Agilex™ 5 Power and I/O State Sequencing
4. Agilex™ 5 Sensor Monitoring System
5. Agilex™ 5 Power Optimization Techniques and Features
6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs

5.1.4.1.2. Power Management and VID Parameters

You can use the following parameters to configure the Power Management and VID interface if the VID operation is in the PMBus Master mode.
Table 21.  Power Management and VID Parameters
Parameters Value Description
Bus speed mode 12 100 KHz Bus speed mode of PMBus interface when operating in the PMBus Master mode.
400 KHz
Slave device type12 TPS53676

Supported device types.

Altera recommends you to use one of the slave device type listed in the drop-down menu that has been tested with the Altera® FPGA tools. If you are not using one of the slave device type listed in the drop-down menu, select Other option. When you select Other option, refer to Table: SmartVID Regulator Requirements, Table: Supported Voltage Output Format for Agilex™ 5 Devices with –V and –E Power Options, and Table: Supported Commands for the PMBus Master Mode for the voltage regulator requirements details.

LTC3882
ISL68223
Other
Device address in PMBus Slave mode13 7-bit hexadecimal value Device address in the PMBus Slave mode.
Number of slave devices 1 to 7, or All Indicates the number of voltage regulator in the system.
PMBus device 0 slave address12 7-bit hexadecimal value

External power regulator address.

This parameter must be non-zero when you are using the PMBus Master mode.
PMBus device 1 slave address12 7-bit hexadecimal value External power regulator address.
PMBus device 2 slave address12 7-bit hexadecimal value External power regulator address.
PMBus device 3 slave address12 7-bit hexadecimal value External power regulator address.
PMBus device 4 slave address12 7-bit hexadecimal value External power regulator address.
PMBus device 5 slave address12 7-bit hexadecimal value External power regulator address.
PMBus device 6 slave address12 7-bit hexadecimal value External power regulator address.
PMBus device 7 slave address12 7-bit hexadecimal value External power regulator address.
Voltage output format12 Direct format

The voltage output format when the operation mode is PMBus Master.

If the voltage output format is the Direct format, you must set the following parameters:

  • Direct format coefficient m
  • Direct format coefficient b
  • Direct format coefficient R

If the voltage regulator is the Linear format, you must set the Linear format N parameter. 14

For more information about the parameters, refer to your selected voltage regulator data sheet.

For all voltage output format, you must also select the correct "translated voltage output unit".
Linear format
Direct format coefficient m12 Signed integer: -32768 to 32767 Direct format coefficient m of the slave device type when the operation mode is PMBus Master. For more information about the coefficient value, refer to the respective voltage regulator data sheet.
Direct format coefficient b12 Signed integer: -32768 to 32767 Direct format coefficient b of the slave device type when the operation mode is PMBus Master. For more information about the coefficient value, refer to the respective voltage regulator data sheet.
Direct format coefficient R12 Signed integer: -128 to 127 Direct format coefficient R of the slave device type when the operation mode is PMBus Master. For more information about the coefficient value, refer to the respective voltage regulator data sheet.
Linear format N12 Signed integer: –16 to 15 Output voltage command when the voltage output format is set to the Linear format.
Translated voltage value unit12 millivolts Indicates the translated output voltage is in millivolts (mV) or volts (V).
volts
Enable PAGE command12 Enable By enabling the PAGE command, the FPGA PMBus Master uses the PAGE command to set all the output channels (0xFF) on registered regulator modules to respond to VOUT_COMMAND. If only specified output channels on registered regulator modules must respond to VOUT_COMMAND, enter the corresponding page value (0x00 – 0xFF).
Disable
Enable status_byte for polling Enable

By enabling the STATUS_BYTE polling in the master mode, the firmware sends the STATUS_BYTE command for every 500 ms. If any errors are found, the STATUS_BYTE pin is asserted. The error message queue (EMQ) provides the full error details.

15
Disable
Diagnostic Boot Enable

The diagnostic boot feature performs additional checks of the configuration and operation of the voltage regulator. This feature adds to the configuration time and should be enabled during the board bring-up operations.

Disable
Disable VID for debug purpose only Enable

This option is for debug purpose only. When you enable this option, you must set the device operating voltage to 0.8 V. VID is disabled, and the device performance and functionality are not guaranteed.

Disable
Related Information
12 This parameter is used for the PMBus Master mode.
13 This parameter is used for the PMBus Slave mode.
14 N is the exponent of a 5-bit two's compliment integer.
15 The SEU_ERROR pin must be enabled in the Quartus® Prime setting to observe the error. The SEU_ERROR signal goes high whenever the error message queue contains one or more error messages. For more information, refer to the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs .
Level Two Title