Power Management User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813161
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Power Management Overview 2. Agilex™ 5 Power Basics 3. Agilex™ 5 Power and I/O State Sequencing 4. Agilex™ 5 Sensor Monitoring System 5. Agilex™ 5 Power Optimization Techniques and Features 6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Agilex™ 5 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Power and Thermal Calculator 2.4. Power Analyzer
3. Agilex™ 5 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Floating Voltage 3.4. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in HSIO, HVIO, HPS IO, and SDM IO Banks During Power Sequencing
3.4. Power-On Reset x
3.4.1. Power Supplies Monitored by the POR Circuitry
4. Agilex™ 5 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function 4.1.2. Voltage Sensor Voltage Reference Pins
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor Catastrophic Trip Signal 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Guidelines: Connecting External Reference to the Agilex™ 5 Voltage Reference Pins 4.3.3. Temperature Monitor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 5 Remote TSD
5. Agilex™ 5 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Agilex™ 5 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Agilex™ 5 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Agilex™ 5 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Agilex™ 5 Power Management Overview
2. Agilex™ 5 Power Basics
3. Agilex™ 5 Power and I/O State Sequencing
4. Agilex™ 5 Sensor Monitoring System
5. Agilex™ 5 Power Optimization Techniques and Features
6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs

4.2.1. Local Temperature Sensor

The Agilex™ 5 local temperature sensors use built-in 11-bit ADCs and provide temperature readouts through the SDM mailbox.

Each temperature sensor location contains up to five local TSDs in the core fabric.

Figure 6.  Agilex™ 5 FPGAs Local Temperature SensorThis figure is a block diagram of the local temperature sensors. For the physical locations of the sensors, refer to the related information.


Agilex™ 5 devices provide up to 4 local temperature sensor locations for monitoring on-chip temperature.

Refer to the related information for more details about the locations and availability of the temperature sensors in different Agilex™ 5 series, densities, and packages.

Catastrophic Trip Signal

The catastrophic trip signal, nCATTRIP, is an optional signal that you can assign to any unused SDM_IO pin. You can set the temperature threshold point for nCATTRIP from 95°C to 120°C, in 1°C increments. To set the temperature threshold point, from the Quartus® Prime menu, navigate to Assignments > Device > Device and Pin Options > General.

If enabled, the nCATTRIP signal transitions high and stays high after the device enters user mode. When the core temperature reaches the threshold that you set, the nCATTRIP signal drives low—you must immediately power down the FPGA to avoid permanent damage to the device. The nCATTRIP signal is only valid after the device enters user mode. Design your system to monitor the nCATTRIP signal only if the FPGA is in user mode and the SDM I/O is configured with the nCATTRIP option enabled in the FPGA design. For example, the FPGA does not enter user mode when being configured using QSPI or the provision helper image; therefore, the nCATTRIP signal should not be monitored in such condition. You must also cease the nCATTRIP signal monitoring when the FPGA reconfiguration is triggered, and resume the nCATTRIP signal monitoring when the FPGA is fully reconfigured.

Note: The catastrophic signal is not supported for the local TSD in the SDM location.
Related Information
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