Power Management User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813161
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Power Management Overview 2. Agilex™ 5 Power Basics 3. Agilex™ 5 Power and I/O State Sequencing 4. Agilex™ 5 Sensor Monitoring System 5. Agilex™ 5 Power Optimization Techniques and Features 6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Agilex™ 5 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Power and Thermal Calculator 2.4. Power Analyzer
3. Agilex™ 5 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Floating Voltage 3.4. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in HSIO, HVIO, HPS IO, and SDM IO Banks During Power Sequencing
3.4. Power-On Reset x
3.4.1. Power Supplies Monitored by the POR Circuitry
4. Agilex™ 5 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function 4.1.2. Voltage Sensor Voltage Reference Pins
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Guidelines: Connecting External Reference to the Agilex™ 5 Voltage Reference Pins 4.3.3. Temperature Monitor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 5 Remote TSD
5. Agilex™ 5 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Agilex™ 5 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Agilex™ 5 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Agilex™ 5 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Agilex™ 5 Power Management Overview
2. Agilex™ 5 Power Basics
3. Agilex™ 5 Power and I/O State Sequencing
4. Agilex™ 5 Sensor Monitoring System
5. Agilex™ 5 Power Optimization Techniques and Features
6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs

5.1.2.2. PMBus Slave Mode

Agilex™ 5 devices can also be configured in the PMBus slave mode with an external power management controller acting as the PMBus master. The external power management controller that interact with Agilex™ 5 devices over PMBus must support clock stretching. The external power management controller is responsible for driving all PMBus transactions, querying the FPGA for its target voltage requirements and interacting with the voltage regulators to configure them to the FPGA's target voltage.

Figure 14. PMBus Slave Mode
Table 16.  Supported Commands for the PMBus Slave Mode
Command Name Command Code Default PMBus Transaction Type Number of Bytes
CLEAR_FAULTS 03h — Write byte 0
VOUT_MODE 20h 40h Read byte 1
VOUT_COMMAND 21h — Read word 2
STATUS_BYTE 78h 00h Read byte 1

For the PMBus slave mode with PWRMGT_ALERT, you must follow the guidelines in the following figures and tables for the external PMBus flow.

Figure 15. Handshake Flow between the External PMBus Master and FPGA in the PMBus Slave Mode with the PWRMGT_ALERT Signal
Table 17.  Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE=0
Sequence SDM PMBus Master Notes
1 Asserts the PWRMGT_ALERT signal — —
2 — Detects the PWRMGT_ALERT signal —
3 — Initiates the ARA flow —
4 Responds to the ARA flow and provides its address — Only the device which has asserted the PWRMGT_ALERT signal in step 1 responds to the ARA flow by providing its address.
5 Deasserts the PWRMGT_ALERT signal — The PWRMGT_ALERT signal is only deasserted after the SDM responds with its address in the ARA flow.
6 — Reads the STATUS_BYTE —
7 Returns STATUS_BYTE=0 — Indicates the FPGA voltage requires an update.
8 — Sends CLEAR_FAULTS —
9 — Sends VOUT_COMMAND The VOUT_COMMAND must be received by the SDM within 200 ms after the PWRMGT_ALERT signal is asserted. Failure to meet this requirement causes configuration error. 10
10 Receives the VOUT_COMMAND, responds with the target voltage — Calculated based on the temperature, the VID fuse and the coefficient for the direct format (you need to specify this input).
11 — Sets the voltage regulator to the target voltage in step size not greater than 10 mV/10 ms step —
Table 18.  Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE is not equal to 0
Sequence SDM PMBus Master Notes
1 Asserts the PWRMGT_ALERT signal — The SDM detects fault and asserts the PWRMGT_ALERT signal. 11
2 — Detects the PWRMGT_ALERT signal —
3 — Initiates the ARA flow —
4 Responds to the ARA flow and provides its address — Only the device which has asserted the PWRMGT_ALERT signal in step 1 responds to the ARA flow by providing its address.
5 Deasserts the PWRMGT_ALERT signal — The PWRMGT_ALERT signal is only deasserted after the SDM responds with its address in the ARA flow.
6 — Reads the STATUS_BYTE —
7 Returns the STATUS_BYTE when not equal to 0 — Indicates that other fault has occurred
8 — Sends CLEAR_FAULTS To reset the STATUS_BYTE.
9 — Reads the STATUS_BYTE To confirm that STATUS_BYTE=0.
10 — External master to handle the faults —
Figure 16. Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram with PWRMGT_ALERT

The Agilex™ 5 devices in the PMBus slave mode sends the VOUT_COMMAND value in the direct format only. To read the actual voltage value, use the following equation to convert the VOUT_COMMAND value from the Agilex™ 5 devices.

Figure 17. Direct Format Equation

The equation shows how to convert the direct format value where:

  • X, is the calculated, real value in mV;
  • m, is the slope coefficient, a 2-byte two's complement integer;
  • Y, is the 2-byte two's complement integer received from the Agilex™ 5 devices;
  • b, is the offset, a 2-byte two's complement integer;
  • R, is the exponent, a 1-byte two's complement integer

The following example shows how an external power management controller retrieves values from the Agilex™ 5 devices. Coefficients used in the VOUT_COMMAND are as follows:

  • m = 1
  • b = 0
  • R = 0

If the external power management controller retrieved a value of 0384h, it is equivalent to the following:

X = (1/1) x (0384h x 10-0 - 0) = 900 mV = 0.90 V

10 The SDM triggers an error when it does not receive VOUT_COMMAND within a specified time. To avoid device configuration failure, you must power cycle the device to recover from the error.
11

The following faults can raise the PWRMGT_ALERT signal:

  • PMBUS_ERR_RD_TOO_MANY_BYTES (Error with the length of the PMBus/I2C message length)
  • PMBUS_ERR_WR_TOO_MANY_BYTES (Error with the length of the PMBus/I2C message length)
  • PMBUS_ERR_UNSUPPORTED_CMD (VOUT_COMMAND, VOUT_MODE, READ_STATUS, and CLEAR_FAULTS are the only supported commands in the PMBUS Slave Mode)
  • PMBUS_ERR_READ_FLAG (Received duplicate command before being able to respond to the first command)
  • PMBUS_ERR_INVALID_DATA (Invalid or malformed PMBus/I2C message)

If any of the above errors are detected, the PWRMGT_ALERT signal is raised and bit 1 of the status register is set.

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