Power Management User Guide: Agilex™ 5 FPGAs and SoCs

ID 813161
Date 7/08/2024
Public
Document Table of Contents

6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Changes
2024.07.08
  • Updated Figure: Relationship Between tRAMP and POR Delay.
  • Added a new topic—Floating Voltage.
  • Updated the Agilex™ 5 Sensor Monitoring System section:
    • Updated Figure: Temperature Sensing Diode Locations.
    • Updated Table: Local Temperature Sensor Locations and Corresponding Bank Names.
    • Updated the Catastrophic Trip Signal information in the Local Temperature Sensor section.
    • Updated support channel for location number 1 in Table: Local Temperature Sensor Locations and Equivalent Remote TSD Pin Names.
    • Updated the information related to the Specify the local TSDs to read function in Table: Sensor Mask Function for Each Local TSD Location.
    • Updated the information related to the temperature from all local TSDs in location 1 and the highest temperature in the location in Table: Examples for Reading Temperature through the SDM Mailbox.
  • Updated the footnote in sequence 9 in Table: Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE=0 for clarity.
  • Made editorial edits throughout the document.
2024.04.01 Initial release.