Power Management User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813161
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Power Management Overview 2. Agilex™ 5 Power Basics 3. Agilex™ 5 Power and I/O State Sequencing 4. Agilex™ 5 Sensor Monitoring System 5. Agilex™ 5 Power Optimization Techniques and Features 6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Agilex™ 5 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Intel® FPGA Power and Thermal Calculator 2.4. Power Analyzer
3. Agilex™ 5 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Floating Voltage 3.4. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in HSIO, HVIO, HPS IO, and SDM IO Banks During Power Sequencing
3.4. Power-On Reset x
3.4.1. Power Supplies Monitored by the POR Circuitry
4. Agilex™ 5 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function 4.1.2. Voltage Sensor Voltage Reference Pins
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Guidelines: Connecting External Reference to the Agilex™ 5 Voltage Reference Pins 4.3.3. Temperature Monitor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 5 Remote TSD
5. Agilex™ 5 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Agilex™ 5 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Agilex™ 5 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Agilex™ 5 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Agilex™ 5 Power Management Overview
2. Agilex™ 5 Power Basics
3. Agilex™ 5 Power and I/O State Sequencing
4. Agilex™ 5 Sensor Monitoring System
5. Agilex™ 5 Power Optimization Techniques and Features
6. Document Revision History for the Power Management User Guide: Agilex™ 5 FPGAs and SoCs

5.1.2.3. Fail Safe Mechanism

If a miscommunication situation happens between the FPGA device and the external voltage regulator, the voltage regulator might be supplying unexpected voltage to the FPGA device.

To avoid voltage supply issue to the FPGA device, a safety net check processing is implemented in the Quartus® Prime software against your input setting (coefficient value—m, b, r for the direct mode and N for the linear mode) in the power management GUI.

The fail safe mechanism detects the early issue during the configuration phase, before the PMBus communication is established with the voltage regulator, prior to any voltage adjustment. If an error occurred, configuration is unsuccessful.

The Quartus® Prime software maintains a list of Altera validated voltage regulator's coefficient values. During configuration, the firmware performs the calculation and conversion based on the information of your selected voltage regulator in the Quartus® Prime GUI to obtain the respective voltage regulator data, using the PMBus Direct or Linear format formula. The calculated data is then compared against the Altera's maintained voltage regulator information in the Quartus® Prime software. If there is no matching data, configuration fails and the VOUT_COMMAND is not sent. However, this safety net check is not applicable when you select the voltage regulator type as "Other" in the Quartus® Prime GUI.

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