Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP User Guide

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ID 683510
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP Overview
1. Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP Overview x
1.1. Release Information 1.2. Device Family Support 1.3. Commands and Responses 1.4. Mailbox Client with Avalon® Streaming Interface Intel FPGA IP User Guide Document Archives 1.5. Document Revision History for the Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP User Guide
1.2. Device Family Support x
1.2.1. Parameters 1.2.2. Interfaces
1.2.2. Interfaces x
1.2.2.1. Clock and Reset Interfaces 1.2.2.2. Command Interface 1.2.2.3. Response Interface 1.2.2.4. Command Status Interface
1.3. Commands and Responses x
1.3.1. Operation Commands 1.3.2. Error Code Responses 1.3.3. Error Code Recovery
1. Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP Overview

1. Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP Overview

Updated for:
Intel® Quartus® Prime Design Suite 24.2
IP Version 2.0.0
The Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP provides a communication channel between your custom logic and the secure device manager (SDM). You can use the Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP to send command packets and receive response packets from SDM peripheral modules. The Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP defines functions that the SDM runs.

Your custom logic can use this communication channel to receive information and access flash memory from only the following peripheral modules:

  • The Chip ID
  • The Temperature Sensor
  • The Voltage Sensor
  • Quad serial peripheral interface (SPI) flash memory
Figure 1.  Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP System Design
The following figure shows an application in which the Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP reads the Chip ID.
Figure 2. Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP Reads Chip ID

Section Content
Release Information
Device Family Support
Commands and Responses
Mailbox Client with Avalon Streaming Interface Intel FPGA IP User Guide Document Archives
Document Revision History for the Mailbox Client with Avalon Streaming Interface Intel FPGA IP User Guide

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