Power Management User Guide: Agilex™ 5 FPGAs and SoCs

ID 813161
Date 7/08/2024
Public
Document Table of Contents

5.2. DSP and M20K Power Gating

Agilex™ 5 devices support power gating for both DSP blocks and M20K memory blocks. By default, the Quartus® Prime software automatically configures unused DSP blocks and M20K memory blocks to be power gated.