Power Management User Guide: Agilex™ 5 FPGAs and SoCs

ID 813161
Date 7/08/2024
Public
Document Table of Contents

3.1. Overview

The Agilex™ 5 devices require a specific power sequence.

This section describes several power management options and discusses proper I/O management during device power up and power down. Design your power supply solution to properly control the complete power sequence. The requirements in this section must be followed to prevent unpredictable current draw to the FPGA device, which can potentially impact the I/O functionality.