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8.3.6.2. Supported LPDDR5 Topologies
In the above figure, all signals from the controller to DRAM package are point-to-point connections.
In the above figure, all signals from the controller to DRAM package are point-to-point connections.
In the above figure, CK, WCK and CA/CS signals from the controller to DRAM are via T-Line connection; each WCK signal from the controller can be connected to both DRAM dies via T-Line, or can be connected to both WCK signals at each DRAM die via T-line.
In the above figure, CK, WCK and CA/CS signals from the controller to DRAM are via T-Line connection.
In the above figure, all signals from the controller to DRAM package are point to point connections, except the CK signal which is connected via T-Line in power mode optimization.
In the above figure, all signals from the controller to DRAM package are point-to-point connections
In the above figure, all signals from the controller to DRAM package are point-to-point connections.
In the above figure, CK, WCK and CA/CS signals are connected to both DRAM dies via T-Line connection.
The following table provides comprehensive routing guidelines (recommended trace impedance and length) for each LPDDR5 signal, based on a memory down topology. For example, the maximum length of the main trace routing can be derived from total trace length by subtracting the break-out and break-in trace segment lengths.
The signal trace width, and minimum spacing/gaps (in mils) from edge-to-edge of signal traces are based on the default stackup shown in the PCB Stack-up and Design Considerations topic; however, PCB designers can use the target impedance for any other stackups. The h value in the table represents the minimum substrate height from signal layer to reference layer.
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Reset signal routing design also follows the CMD/ADD/CTRL routing design. Maintain at least 5x h edge-to-edge spacing from the Reset signal to other signals on the same layer. There is no requirement to have skew matching between Reset signal and CLK signal.
Skew matching for the LPDDR5 interface consists of both package routing skew and PCB physical routing skew. You must maintain skew matching of CA and CTRL with respect to the clock signals to ensure signals at the receiver are correctly sampled. In addition, there are skew matching requirements for DQ and DQS within a byte group, DQS and CLK.
The following table provides a detailed skew matching guideline to facilitate PCB trace routing efforts. The length matching criteria in the table below represents a default PCB on an Altera platform board design. Skew matching criteria must be always followed in any other stackup.
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LPDDR5 eye margin is sensitive to crosstalk, especially when the signals are routed on deep layers in the stackup. The deep-layer vertical transition induces more vertical coupling between signals and hence more crosstalk.
Altera recommends keeping the via transition depth in Z-direction to less than 16mil (routed on shallow layers with backdrill) to achieve high performance on the LPDDR5 interface. The maximum data rate of LPDDR5 depends on the type of PCB and on the DDR memory down configuration as seen in the following table.
Memory | LPDDR5 | |
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Signal; Group | DQ | |
Board Thickness (mil) | 65mil or 120mil (Routing must be on upper layers, max via transition depth <=16mil) | 65mil or 120mil (Routing must be on upper layers, max via transition depth <=16mil) |
Maximum Z-transition height (mil) | 16 | 16 |
PCB Stripline Trace Impedance (Ohms) | 40 | 40 |
Memory Configuration | Memory Down | Memory Down |
# of Rank | 1 (x16 bit or x32 bit Double Die) | 2 (x 16 or x 32 bit) |
Maximum Length Total (Inch) | 3.0 | 3.0 |
Notes | Maximum package length in FPGA design is shorter than 34mm. |