External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

4.4.2. s0_axi4lite_rst_n for External Memory Interface Calibration Component

Axilite reset interface

Table 57.  Interface: s0_axi4lite_rst_nInterface type: reset
Port Name Direction Description
s0_axi4lite_rst_n input Axilite reset