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1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide
3.1.1. Agilex™ 7 M-Series EMIF Architecture: I/O Subsystem
3.1.2. Agilex™ 7 M-Series EMIF Architecture: I/O SSM
3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank
3.1.4. Agilex™ 7 M-Series EMIF Architecture: I/O Lane
3.1.5. Agilex™ 7 M-Series EMIF Architecture: Input DQS Clock Tree
3.1.6. Agilex™ 7 M-Series EMIF Architecture: PHY Clock Tree
3.1.7. Agilex™ 7 M-Series EMIF Architecture: PLL Reference Clock Networks
3.1.8. Agilex™ 7 M-Series EMIF Architecture: Clock Phase Alignment
3.1.9. User Clock in Different Core Access Modes
4.1.1. ref_clk for External Memory Interfaces (EMIF) IP
4.1.2. core_init_n for External Memory Interfaces (EMIF) IP
4.1.3. usr_async_clk for External Memory Interfaces (EMIF) IP
4.1.4. usr_clk for External Memory Interfaces (EMIF) IP
4.1.5. usr_rst_n for External Memory Interfaces (EMIF) IP
4.1.6. s0_axi4 for External Memory Interfaces (EMIF) IP
4.1.7. mem for External Memory Interfaces (EMIF) IP
4.1.8. oct for External Memory Interfaces (EMIF) IP
4.2.1. ref_clk for External Memory Interfaces (EMIF) IP
4.2.2. core_init_n for External Memory Interfaces (EMIF) IP
4.2.3. usr_async_clk for External Memory Interfaces (EMIF) IP
4.2.4. usr_clk for External Memory Interfaces (EMIF) IP
4.2.5. usr_rst_n for External Memory Interfaces (EMIF) IP
4.2.6. s0_axi4 for External Memory Interfaces (EMIF) IP
4.2.7. mem for External Memory Interfaces (EMIF) IP
4.2.8. i3c for External Memory Interfaces (EMIF) IP
4.2.9. mem_lbd for External Memory Interfaces (EMIF) IP
4.2.10. mem_lbs for External Memory Interfaces (EMIF) IP
4.2.11. oct for External Memory Interfaces (EMIF) IP
4.3.1. ref_clk for External Memory Interfaces (EMIF) IP
4.3.2. core_init_n for External Memory Interfaces (EMIF) IP
4.3.3. usr_async_clk for External Memory Interfaces (EMIF) IP
4.3.4. usr_clk for External Memory Interfaces (EMIF) IP
4.3.5. usr_rst_n for External Memory Interfaces (EMIF) IP
4.3.6. s0_axi4 for External Memory Interfaces (EMIF) IP
4.3.7. mem for External Memory Interfaces (EMIF) IP
4.3.8. oct for External Memory Interfaces (EMIF) IP
6.2.4.1. Address and Command Pin Placement for DDR4
6.2.4.2. DDR4 Data Width Mapping
6.2.4.3. General Guidelines - DDR4
6.2.4.4. x4 DIMM Implementation
6.2.4.5. Specific Pin Connection Requirements
6.2.4.6. Command and Address Signals
6.2.4.7. Clock Signals
6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3.5.1. Single Rank x 8 Discrete (Component) Topology
6.3.5.2. Single Rank x 16 Discrete (Component) Topology
6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies
6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations
6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations
6.3.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
7.3.1. PCB Stack-up and Design Considerations
7.3.2. General Design Considerations
7.3.3. DDR Differential Signals Routing
7.3.4. Ground Plane and Return Path
7.3.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines
7.3.6. DRAM Break-in Layout Guidelines
7.3.7. DDR5 PCB Layout Guidelines
7.3.8. DDR5 Simulation Strategy
7.3.7.1. DDR5 Discrete Component/Memory Down Topology: up to 40-Bit Interface (1 Rank x8 or x16, 2 Rank x8 or x16)
7.3.7.2. Routing Guidelines for DDR5 Memory Down: 1 Rank or 2 Rank (x8 bit or x16 bit) Configurations
7.3.7.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations
7.3.7.4. Example of a DDR5 layout on an Altera FPGA Platform Board
11.1. Interface Configuration Performance Issues
11.2. Functional Issue Evaluation
11.3. Timing Issue Characteristics
11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer
11.5. Debugging with the External Memory Interface Debug Toolkit
11.6. Generating Traffic with the Test Engine IP
11.7. Guidelines for Developing HDL for Traffic Generator
11.8. Guidelines for Traffic Generator Status Check
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8.2.4.3. LPDDR5 Byte Lane Swapping
The data lane can be swapped when the byte-lanes are utilized as DQ/DQS pins. Byte lane swapping on utilized lanes is allowed when you swap all the DQ/DQS/DM pins in the same byte lane with the other utilized byte lane.
The rules for swapping DQ byte lane are as follows:
- You can only swap between utilized DQ lanes.
- You cannot swap a DQ lane with an AC lane.
- Additional restrictions apply when you use a x16 memory component:
- You must place DQ group 0 and DQ group 1 on adjacent byte lanes, unless they are separated by AC lanes. These 2 groups must be connected to the same x16 memory component.
- You must place DQ group 2 and DQ group 3 on adjacent byte lanes, unless they are separated by AC lanes. These 2 groups must be connected to the same x16 memory component.
- If you use only one byte of the x16 memory component, you must use only the lower byte of the memory component.
Controller | Data Width Usage | BL7 P95:P84 | BL6 P83:P72 | BL5 P71:P60 | BL4 P59:P48 | BL3 P47:P36 | BL2 P35:P24 | BL1 P23:P12 | BL0 P11:P0 |
---|---|---|---|---|---|---|---|---|---|
Primary & Secondary | LPDDR5 2ch x16 | DQ[1] S | DQS[0] S | AC1 S | AC0 S | AC1 P | AC0 P | DQ[1] P | DQ[0] P |
Primary | LPDDR5 x32 | DQ[3] P | DQ[2] P | GPIO | GPIO | AC1 P | AC0 P | DQ[1] P | DQ[0] P |
Note:
|
Example 1: LPDDR5 2 ch x16
DQ[0] and DQ[1] of the primary controller are can swapped with each other. DQ[0] and DQ[1] of the secondary controller can be swapped with each other.
Example 2: LPDDR5 x32
DQ[0] and DQ[1] can be swapped with each other. DQ[2] and DQ[3] can be swapped with each other.