External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

8.2.4.3. LPDDR5 Byte Lane Swapping

The data lane can be swapped when the byte-lanes are utilized as DQ/DQS pins. Byte lane swapping on utilized lanes is allowed when you swap all the DQ/DQS/DM pins in the same byte lane with the other utilized byte lane.

The rules for swapping DQ byte lane are as follows:

  • You can only swap between utilized DQ lanes.
  • You cannot swap a DQ lane with an AC lane.
  • Additional restrictions apply when you use a x16 memory component:
    • You must place DQ group 0 and DQ group 1 on adjacent byte lanes, unless they are separated by AC lanes. These 2 groups must be connected to the same x16 memory component.
    • You must place DQ group 2 and DQ group 3 on adjacent byte lanes, unless they are separated by AC lanes. These 2 groups must be connected to the same x16 memory component.
    • If you use only one byte of the x16 memory component, you must use only the lower byte of the memory component.
Table 176.  Component
Controller Data Width Usage BL7 P95:P84 BL6 P83:P72 BL5 P71:P60 BL4 P59:P48 BL3 P47:P36 BL2 P35:P24 BL1 P23:P12 BL0 P11:P0
Primary & Secondary LPDDR5 2ch x16 DQ[1] S DQS[0] S AC1 S AC0 S AC1 P AC0 P DQ[1] P DQ[0] P
Primary LPDDR5 x32 DQ[3] P DQ[2] P GPIO GPIO AC1 P AC0 P DQ[1] P DQ[0] P
Note:
  • P Primary controller.
  • S Secondary controller.

Example 1: LPDDR5 2 ch x16

DQ[0] and DQ[1] of the primary controller are can swapped with each other. DQ[0] and DQ[1] of the secondary controller can be swapped with each other.

Example 2: LPDDR5 x32

DQ[0] and DQ[1] can be swapped with each other. DQ[2] and DQ[3] can be swapped with each other.