External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

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ID 772538
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction 3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture 4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals 5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support 7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support 8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support 9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure 10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization 11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging 12. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction x
2.1. Agilex™ 7 M-Series EMIF IP Protocol and Feature Support 2.2. Agilex™ 7 M-Series EMIF IP Design Flow 2.3. Agilex™ 7 M-Series EMIF IP Design Checklist
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction 3.2. Agilex™ 7 M-Series EMIF Sequencer 3.3. Agilex™ 7 M-Series EMIF Controller 3.4. Agilex™ 7 M-Series EMIF IP for Hard Processor Subsystem (HPS)
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction x
3.1.1. Agilex™ 7 M-Series EMIF Architecture: I/O Subsystem 3.1.2. Agilex™ 7 M-Series EMIF Architecture: I/O SSM 3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank 3.1.4. Agilex™ 7 M-Series EMIF Architecture: I/O Lane 3.1.5. Agilex™ 7 M-Series EMIF Architecture: Input DQS Clock Tree 3.1.6. Agilex™ 7 M-Series EMIF Architecture: PHY Clock Tree 3.1.7. Agilex™ 7 M-Series EMIF Architecture: PLL Reference Clock Networks 3.1.8. Agilex™ 7 M-Series EMIF Architecture: Clock Phase Alignment 3.1.9. User Clock in Different Core Access Modes
3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank x
3.1.3.1. Lockstep Configuration 3.1.3.2. DDR4 Pin Placement 3.1.3.3. DDR5 Pin Placement 3.1.3.4. LPDDR5 Pin Placement 3.1.3.5. I/O Sub-Bank Usage
3.2. Agilex™ 7 M-Series EMIF Sequencer x
3.2.1. Agilex™ 7 M-Series Mailbox Structure and Register Definitions
3.2.1. Agilex™ 7 M-Series Mailbox Structure and Register Definitions x
3.2.1.1. Mailbox Supported Commands 3.2.1.2. Mailbox Command Definitions
3.3. Agilex™ 7 M-Series EMIF Controller x
3.3.1. Hard Memory Controller
3.3.1. Hard Memory Controller x
3.3.1.1. Hard Memory Controller Features
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals x
4.1. Agilex™ 7 M-Series EMIF IP Interfaces for DDR4 4.2. Agilex™ 7 M-Series EMIF IP Interfaces for DDR5 4.3. Agilex™ 7 M-Series EMIF IP Interfaces for LPDDR5 4.4. Agilex™ 7 M-Series EMIF IP Interfaces for Calibration Component
4.1. Agilex™ 7 M-Series EMIF IP Interfaces for DDR4 x
4.1.1. ref_clk for External Memory Interfaces (EMIF) IP 4.1.2. core_init_n for External Memory Interfaces (EMIF) IP 4.1.3. usr_async_clk for External Memory Interfaces (EMIF) IP 4.1.4. usr_clk for External Memory Interfaces (EMIF) IP 4.1.5. usr_rst_n for External Memory Interfaces (EMIF) IP 4.1.6. s0_axi4 for External Memory Interfaces (EMIF) IP 4.1.7. mem for External Memory Interfaces (EMIF) IP 4.1.8. oct for External Memory Interfaces (EMIF) IP
4.2. Agilex™ 7 M-Series EMIF IP Interfaces for DDR5 x
4.2.1. ref_clk for External Memory Interfaces (EMIF) IP 4.2.2. core_init_n for External Memory Interfaces (EMIF) IP 4.2.3. usr_async_clk for External Memory Interfaces (EMIF) IP 4.2.4. usr_clk for External Memory Interfaces (EMIF) IP 4.2.5. usr_rst_n for External Memory Interfaces (EMIF) IP 4.2.6. s0_axi4 for External Memory Interfaces (EMIF) IP 4.2.7. mem for External Memory Interfaces (EMIF) IP 4.2.8. i3c for External Memory Interfaces (EMIF) IP 4.2.9. mem_lbd for External Memory Interfaces (EMIF) IP 4.2.10. mem_lbs for External Memory Interfaces (EMIF) IP 4.2.11. oct for External Memory Interfaces (EMIF) IP
4.3. Agilex™ 7 M-Series EMIF IP Interfaces for LPDDR5 x
4.3.1. ref_clk for External Memory Interfaces (EMIF) IP 4.3.2. core_init_n for External Memory Interfaces (EMIF) IP 4.3.3. usr_async_clk for External Memory Interfaces (EMIF) IP 4.3.4. usr_clk for External Memory Interfaces (EMIF) IP 4.3.5. usr_rst_n for External Memory Interfaces (EMIF) IP 4.3.6. s0_axi4 for External Memory Interfaces (EMIF) IP 4.3.7. mem for External Memory Interfaces (EMIF) IP 4.3.8. oct for External Memory Interfaces (EMIF) IP
4.4. Agilex™ 7 M-Series EMIF IP Interfaces for Calibration Component x
4.4.1. s0_axi4lite_clk for External Memory Interface Calibration Component 4.4.2. s0_axi4lite_rst_n for External Memory Interface Calibration Component 4.4.3. s0_axil for External Memory Interface Calibration Component
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support x
6.1. Agilex™ 7 M-Series FPGA EMIF IP Parameters for DDR4 6.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 6.3. DDR4 Board Design Guidelines
6.1. Agilex™ 7 M-Series FPGA EMIF IP Parameters for DDR4 x
6.1.1. Agilex™ 7 M-Series FPGA EMIF IP Parameter Descriptions for DDR4 6.1.2. Agilex™ 7 M-Series FPGA EMIF Memory Device IP Parameter Descriptions for DDR4 6.1.3. Agilex™ 7 M-Series FPGA EMIF Calibration IP Parameter Descriptions
6.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
6.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 6.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 6.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 6.2.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP
6.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
6.2.1.1. Estimating Pin Requirements 6.2.1.2. DIMM Options 6.2.1.3. Maximum Number of Interfaces
6.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
6.2.2.1. OCT 6.2.2.2. PLL
6.2.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP x
6.2.4.1. Address and Command Pin Placement for DDR4 6.2.4.2. DDR4 Data Width Mapping 6.2.4.3. General Guidelines - DDR4 6.2.4.4. x4 DIMM Implementation 6.2.4.5. Specific Pin Connection Requirements 6.2.4.6. Command and Address Signals 6.2.4.7. Clock Signals 6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. DDR4 Board Design Guidelines x
6.3.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices 6.3.2. General Layout Routing Guidelines 6.3.3. Reference Stackup 6.3.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.3.5. DDR4 Routing Guidelines: Discrete (Component) Topologies
6.3.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices x
6.3.1.1. Dynamic On-Chip Termination (OCT) 6.3.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.3.1.3. Choosing Terminations on Agilex™ 7 M-Series FPGA Devices 6.3.1.4. On-Chip Termination Recommendations for Agilex™ 7 M-Series FPGA Devices
6.3.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.3.4.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, and SODIMM DDR4 Topologies 6.3.4.2. Skew Matching Guidelines for DIMM Configurations 6.3.4.3. Power Delivery Recommendations for the Memory / DIMM Side
6.3.5. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.3.5.1. Single Rank x 8 Discrete (Component) Topology 6.3.5.2. Single Rank x 16 Discrete (Component) Topology 6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies 6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations 6.3.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
6.3.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
6.3.5.6.1. DDR4 Byte Lane Swapping 6.3.5.6.2. DDR4 Address and Command and CLK Lane 6.3.5.6.3. DDR4 Interface x8 Data Lane 6.3.5.6.4. DDR4 Interface x4 Data Lane 6.3.5.6.5. Pin Swizzling
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support x
7.1. Agilex™ 7 M-Series FPGA EMIF IP Parameters for DDR5 7.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 7.3. DDR5 Board Design Guidelines
7.1. Agilex™ 7 M-Series FPGA EMIF IP Parameters for DDR5 x
7.1.1. Agilex™ 7 M-Series FPGA EMIF IP Parameter Descriptions for DDR5 7.1.2. Agilex™ 7 M-Series FPGA EMIF Memory Device IP Parameter Descriptions for DDR5 7.1.3. Agilex™ 7 M-Series FPGA EMIF Calibration IP Parameter Descriptions
7.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
7.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 7.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 7.2.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP 7.2.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
7.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. DIMM Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
7.2.3.1. General Guidelines - DDR5 7.2.3.2. x4 DIMM Implementation 7.2.3.3. Specific Pin Connection Requirements 7.2.3.4. Command and Address Signals 7.2.3.5. Clock Signals 7.2.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.2.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP x
7.2.4.1. Address and Command Pin Placement for DDR5 7.2.4.2. DDR5 Data Width Mapping
7.2.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
7.2.5.1. DDR5 Byte Lane Swapping 7.2.5.2. DDR5 Address and Command and CLK Lane 7.2.5.3. DDR5 Interface x8 Data Lane 7.2.5.4. DDR5 Interface x4 Data Lane 7.2.5.5. Pin Swizzling
7.3. DDR5 Board Design Guidelines x
7.3.1. PCB Stack-up and Design Considerations 7.3.2. General Design Considerations 7.3.3. DDR Differential Signals Routing 7.3.4. Ground Plane and Return Path 7.3.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines 7.3.6. DRAM Break-in Layout Guidelines 7.3.7. DDR5 PCB Layout Guidelines 7.3.8. DDR5 Simulation Strategy
7.3.7. DDR5 PCB Layout Guidelines x
7.3.7.1. DDR5 Discrete Component/Memory Down Topology: up to 40-Bit Interface (1 Rank x8 or x16, 2 Rank x8 or x16) 7.3.7.2. Routing Guidelines for DDR5 Memory Down: 1 Rank or 2 Rank (x8 bit or x16 bit) Configurations 7.3.7.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations 7.3.7.4. Example of a DDR5 layout on an Altera FPGA Platform Board
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support x
8.1. Agilex™ 7 M-Series FPGA EMIF IP Parameters for LPDDR5 8.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR5 Board Design Guidelines
8.1. Agilex™ 7 M-Series FPGA EMIF IP Parameters for LPDDR5 x
8.1.1. Agilex™ 7 M-Series FPGA EMIF IP Parameter Descriptions for LPDDR5 8.1.2. Agilex™ 7 M-Series FPGA EMIF Memory Device IP Parameter Descriptions for LPDDR5 8.1.3. Agilex™ 7 M-Series FPGA EMIF Calibration IP Parameter Descriptions
8.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 8.2.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP
8.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. DIMM Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
8.2.3.1. General Guidelines - LPDDR5 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals
8.2.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP x
8.2.4.1. Address and Command Pin Placement for LPDDR5 8.2.4.2. LPDDR5 Data Width Mapping 8.2.4.3. LPDDR5 Byte Lane Swapping
8.3. LPDDR5 Board Design Guidelines x
8.3.1. PCB Stack-up and Design Considerations 8.3.2. General Design Considerations 8.3.3. DDR Differential Signals Routing 8.3.4. Ground Plane and Return Path 8.3.5. DRAM Break-in Layout Guidelines 8.3.6. LPDDR5 PCB Layout Guidelines 8.3.7. LPDDR5 Simulation Strategy
8.3.6. LPDDR5 PCB Layout Guidelines x
8.3.6.1. LPDDR5 Discrete Component/Memory Down Topology (1 Rank or 2 Rank, up to 64 Bit Interface) 8.3.6.2. Supported LPDDR5 Topologies 8.3.6.3. Example of an LPDDR5 Layout on an Altera® FPGA Platform Board
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Frequency of Operation 10.4.2. Series of Reads or Writes 10.4.3. AXI to Memory Mapping
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Debugging with the External Memory Interface Debug Toolkit 11.6. Generating Traffic with the Test Engine IP 11.7. Guidelines for Developing HDL for Traffic Generator 11.8. Guidelines for Traffic Generator Status Check
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Altera IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.5. Debugging with the External Memory Interface Debug Toolkit x
11.5.1. Prerequisites for Using the EMIF Debug Toolkit 11.5.2. Configuring Your Design to Use the EMIF Debug Toolkit 11.5.3. Launching the EMIF Debug Toolkit 11.5.4. Using the EMIF Debug Toolkit
11.5.4. Using the EMIF Debug Toolkit x
11.5.4.1. Rerunning Calibration 11.5.4.2. Rerunning the Test Engine 11.5.4.3. Saving Debug Print 11.5.4.4. Calibration Reports 11.5.4.5. Driver Margining Tab 11.5.4.6. Pin Delay Settings Tab
11.8. Guidelines for Traffic Generator Status Check x
11.8.1. Status Check Using the Signal Tap Logic Analyzer 11.8.2. Exporting the Status Interface to the Top-Level Design
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

6.2.4.3. General Guidelines - DDR4

Observe the following general guidelines when placing pins for your Agilex™ 7 M-Series external memory interface.
Note:
  • EMIF IP pin-out requirements for the Agilex™ 7 M-Series Hard Processor Subsystem (HPS) are more restrictive than for a non-HPS memory interface. The HPS EMIF IP defines a fixed pin-out in the Quartus® Prime Pro Edition IP file (.qip), based on the IP configuration.
  1. Ensure that the pins of a single external memory interface reside on the same edge I/O.
  2. The address and command pins and their associated clock pins in the address and command bank must follow a fixed pin-out scheme, as defined in the table in the Address and Command Pin Placement for DDR4 topic.
  3. Not every byte lane can function as an address and command lane or a data lane. The pin assignment must adhere to the DDR4 data width mapping defined in DDR4 Data Width Mapping .
  4. A byte lane must not be used by both address and command pins and data pins.
  5. An I/O 96 bank cannot be used for more than one interface – meaning that two sub-banks belonging to two different EMIF interfaces are not permitted.
  6. Sharing of byte lanes within a sub-bank for two different interfaces is not permitted; you can assign byte lanes within a sub-bank to one EMIF interface only.
  7. Any pin in the same bank that is not used by an external memory interface may not be available for use as a general purpose I/O pin.
    • For fabric EMIF, unused pins in an I/O lane assigned to an EMIF interface cannot be used as general-purpose I/O pins. In the same sub-bank, pins in an I/O lane that is not assigned to an EMIF interface, can be used as general purpose I/O pins.
    • For HPS EMIF, unused pins in an I/O lane assigned to an EMIF interface cannot be used as general-purpose I/O pins. In the same bank, pins in an I/O lane that is not assigned to an EMIF interface cannot be used as general purpose I/O pins either.
    • When the network-on-a-chip (NoC) is used, the use of initiator may block the byte lane in the I/O bank adjacent to the sector where the initiator is located:
      • initiator 0 blocks the access for byte lane (or I/O lane) BL4, BL5, BL6, and partial BL7 (pin index 48 to 88 in the IO96 bank).
      • initiator 1 blocks the access to the fabric AXI command/control port for the primary/secondary controller in the same I/O bank, making the hard controller unavailable for EMIF purposes.
      • initiator 2 blocks the access for BL0,1,2,3 (P0 to P47).
  8. All address and command pins and their associated clock pins (CK and CK#) must reside within a single sub-bank. Refer to the table in DDR4 Data Width Mapping for the supported address and command and data lane placements for DDR4.
  9. An external memory interface can occupy one or more banks on the same edge. When an interface must occupy multiple banks, ensure the following:
    • That the banks are adjacent to one another.
    • That you used only the supported data width mapping as defined in the DDR4 Data Width Mapping table in the DDR4 Data Width Mapping topic. Be aware that not every byte lane can be used as an address and command lane or a data lane.
    • That for lockstep configuration, you used only supported configuration as defined in the Supported DDR4 Mapping for Lockstep Configuration for x64 and Supported Lockstep configuration for DDR4 x72 or x64 (with ECC) tables in the DDR4 Data Width Mapping topic.
  10. Place read data groups according to the DQS grouping in the pin table and the Pin Planner. Read data strobes (such as DQS and DQS#) must reside at physical pins capable of functioning as DQS/CQ and DQSn/CQn for a specific read data group size. You must place the associated read data pins (such as DQ and Q), within the same group.
    Note: For DDR4 interfaces with x4 components, you can use the strobe pins with either of the upper or lower DQ nibbles that are placed within a x8 DQS group in an I/O lane. You must place the DQ pins and associated strobes entirely in either the upper or lower half of a 12-bit bank sub-group.
    Consult the pin table for your device to identify the association between DQ pins and DQS pins for x4 mode operation. Additional restrictions apply for x4/x8 DIMM interoperability.
  11. One of the sub-banks in the device (typically the left sub-bank within corner Bank 3A) may not be available if you use certain device configuration schemes. For some schemes, there may be one byte lane available for EMIF data group:
    • AVST-8 – This is contained entirely within the SDM, therefore all lanes of sub-bank 3A can be used by the external memory interface.
    • AVST-32 – Byte lanes 4, 5, 6, and 7 are all effectively occupied and are not usable by the external memory interface.
    • AVST-16 – Byte lanes 6 contains SDM_DATA[25:16], and is not used by AVSTx16. However, the external memory interface cannot use byte lane 6 when byte lanes 4 and 5 are not usable for EMIF purposes.
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