External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction

The Agilex™ 7 M-Series EMIF architecture contains many new hardware features designed to meet the high-speed requirements of emerging memory protocols, while consuming the smallest amount of core logic area and power.
Note: The current version of the External Memory Interfaces Agilex™ 7 M-Series FPGA IP supports the DDR4, DDR5, and LPDDR5 memory protocols.

The following are key hardware features of the Agilex™ 7 M-Series EMIF architecture:

Hard Sequencer

The sequencer employs a hardened processor, and can perform memory calibration for a wide range of protocols. For Agilex™ 7 M-Series devices, the sequencer and calibration are localized to each I/O bank.

Note: You cannot use the hardened processor for any user applications after calibration is complete.

Hard PHY

The PHY circuitry in Agilex™ 7 M-Series devices is hardened in the silicon, which simplifies the challenges of achieving timing closure and minimizing power consumption.

Hard Memory Controller

The hard memory controller reduces latency and minimizes core logic consumption in the external memory interface. The hard memory controller supports the DDR4, DDR5, and LPDDR5 memory protocols.

High-Speed PHY Clock Tree

Dedicated high speed PHY clock networks clock the I/O buffers in Agilex™ 7 M-Series EMIF IP. The PHY clock trees exhibit low jitter and low duty cycle distortion, maximizing the data valid window.

Automatic Clock Phase Alignment

Automatic clock phase alignment circuitry dynamically adjusts the clock phase of core clock networks to match the clock phase of the PHY clock networks. The clock phase alignment circuitry minimizes clock skew that can complicate timing closure in transfers between the FPGA core and the periphery.

Network-on-Chip (NoC) Interface

The Agilex™ 7 M-Series EMIF IP supports a new Network-on-Chip (NoC) interface. Each IO96 bank contains two 256-bit AXI4 targets and one 32-bit AXI4-Lite target that connect to the NoC. NoC segments span one FPGA clock sector and consists of three AXI4 initiators on the FPGA fabric side. A network of switches transfer packets horizontally across the high-speed interconnect NoC and connect the initiators and targets. Refer to the NoC User Guide for additional information.