External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

12. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.07.08 24.2 6.2.0
  • In the End-User Signals chapter, implemented minor updates to the interface description topics.
  • In the DDR4 Support, DDR5 Support, and LPDDR5 Support chapters, implemented minor updates to the parameter description topics.
  • In the Controller Optimization chapter, added the AXI to Memory Mapping topic.
  • In the Debugging chapter, added the Guidelines for Traffic Generator Status Check section.
  • Implemented minor editorial improvements and branding changes throughout.
2024.04.01 24.1 6.1.0
  • In the Product Architecture chapter:
    • Expanded the note after the table in the LPDDR5 Pin Placement topic.
    • Added two rows to the table in the Mailbox Supported Commands topic.
    • Added two new rows to the Command Definitions table in the Mailbox Command Definitions topic.
  • In the Agilex™ 7 FPGA EMIF IP Parameter for DDR4 topic in the DDR4 Support chapter:
    • Repositioned the Group: Example Design / Example Design table.
    • Added a row to the Group: General IP Parameters / High-Level Parameters table.
    • Added the Group: Example Design / Traffic Generator Program table.
  • In the DDR5 Support chapter:
    • In the Agilex™ 7 FPGA EMIF IP Parameter for DDR5 topic:
      • Repositioned the Group: Example Design / Example Design table.
      • Added the Group: Example Design / Traffic Generator Program table.
    • In the Agilex™ 7 FPGA EMIF Memory Device Description IP (DDR5) Parameter Descriptions topic, added one row to the Group: Memory Timing Parameters / Timing Parameters table.
  • In the LPDDR5 Support chapter:
    • In the Agilex™ 7 FPGA EMIF IP Parameter for LPDDR5 topic:
      • Repositioned the Group: Example Design / Example Design table.
      • Added the Group: Example Design / Traffic Generator Program table.
    • In the Agilex™ 7 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions topic:
      • In the Group: High-Level Parameters table:
        • Changed the Number of Channels in Memory Package row to Number of Channels.
        • Changed the Number of Ranks per Channel row to Memory Ranks.
        • Changed the Number of Individual DRAM Components per Rank row to Number of Components per Rank.
Document Version Quartus® Prime Version IP Version Changes
     
  • In the Debugging chapter:
    • Removed the final sentence from the Interface Configuration Bottleneck and Efficiency Issues topic.
    • In the Debugging with the External Memory Interface Debug Toolkit section, implemented assorted updates and figure replacements in the following topics:
      • Debugging with the External Memory Interface Debug Toolkit.
      • Configuring Your Design to Use the EMIF Debug Toolkit.
      • Launching the EMIF Debug Toolkit.
      • Using the EMIF Debug Toolkit.
      • Rerunning Calibration.
      • Rerunning the Test Engine.
2023.12.04 23.4 6.0.0
  • In the Architecture chapter:
    • In the Mailbox Command Definitions topic, modified the CMD_TARGET_IP_TYPE description in the CMD_REQ Definition table, and added the CMD_TARGET_IP_TYPE Definition table.
  • In the End-User Signals chapter, updated interfaces and signals descriptions.
  • In the DDR4 Support, DDR5 Support, and LPDDR5 Support chapters, updated the parameter description sections.
  • In the LPDDR5 Support chapter:
    • In the LPDDR5 Data Width Mapping topic, modified the Component table.
    • Added the LPDDR5 Byte Lane Swapping topic.
  • In the Debugging chapter:
    • Modified the bulleted lists in the Debugging with the External Memory Interface Debug Toolkit topic.
    • Updated figures in the Rerunning the Traffic Generator and Saving Debug Print topics.
    • Added Calibration Reports, Driver Margining Tab, and Pin Delay Settings Tab topics, to the Debugging with the External Memory Interface Debug Toolkit section.
    • Added the LPDDR5 Byte Lane Swapping topic.
2023.10.02 23.3 5.0.0
  • In the Architecture chapter:
    • Added the Lockstep Configuration topic.
    • Added information to the table in the Mailbox Supported Commands topic.
    • Added three tables to the Mailbox Command Definitions topic.
  • In the DDR4 Support chapter:
    • Added lockstep configuration information to the DDR4 Data Width Mapping topic.
    • Added lockstep configuration information to the General Guidelines - DDR4 topic.
    • Added lockstep configuration information to the DDR4 Byte Lane Swapping topic.
  • In the End-User Signals chapter, updated the s0_axi4 for EMIF topic in the DDR4 Interfaces, DDR5 Interfaces, and LPDDR5 Interfaces sections.
  • In the DDR5 Support chapter, added the Board Design Guidelines section.
  • In the LPDDR5 Support chapter, added the Board Design Guidelines section.
  • In the Debugging chapter, added the Debugging with the External Memory Interface Debug Toolkit section.
2023.06.26 23.2 4.0.0
  • In the Architecture chapter:
    • Added the User Clock in Different Core Access Modes topic.
    • Added the Mailbox Supported Commands and Mailbox Command Definitions topics.
    • Added the Intel Agilex® 7 M-Series EMIF IP for Hard Processor Subsystem (HPS) topic.
  • In the End-User Signals chapter, updated the signals description topics.
  • In the DDR4 Support chapter:
    • Updated the parameter description topics.
    • Modified the DDR4 Byte Lane Swapping topic.
  • In the DDR5 Support chapter:
    • Updated the parameter description topics.
    • Added the Address and Command Pin Placement for DDR5 and DDR5 Data Width Mapping topics.
    • Added the Pin Swapping Guidelines section.
  • In the LPDDR5 Support chapter:
    • Updated the parameter description topics.
    • Added the Address and Command Pin Placement for LPDDR5 and LPDDR5 Data Width Mapping topics.
2023.04.03 23.1 3.0.0 Initial release.