External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

11.6. Generating Traffic with the Test Engine IP

Every Agilex™ 7 M-Series FPGA EMIF design example includes an instance of the software-driven programmable AXI traffic generator, known as the Test Engine IP.

You can view the Test Engine IP software within the following Python scripts:

  • A main.py file that parses the .qsys file and selects the traffic program to run during execution.
  • A traffic_patterns.py file that contains many different tutorial programs and functional tests that you can refer to when writing your own traffic patterns.

For the EMIF design example, the hard-coded traffic program selected when you generate a design is the emif_tg_emulation traffic program, which provides these features:

  • Single write and read (with AxLEN=axlen_a 1 )
  • Single write and read (with AxLEN=axlen_b 2 )
  • Sequential address 3 block of 512 writes and 512 reads (with AxLEN=axlen_a 1 )
  • Sequential address 3 block of 512 writes and 512 reads (with AxLEN=axlen_b 2 )
  • Random address 4 block of 512 writes and 512 reads (with AxLEN= axlen_a 1 )
1 The axlen_a value is dependent on the memory technology:
  • For DDR4: 0
  • For DDR5: 1
  • For LPDDR5: 3
2 The axlen_b value is dependent on the memory technology:
  • For DDR4: 0
  • For DDR5: 0 (results in Read-Modify-Write or Data-Masking on the memory side).
  • For LPDDR5: 3
3 Sequential Address pattern starts at address=0, and increments by (AXI_DATA_WIDTH/8)*(AxLEN+1) on each transaction.
4 Random Address pattern starts at address=0, and uses pseudo-random addresses.