External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

11.8. Guidelines for Traffic Generator Status Check

The Test Engine IP allows you to observe traffic generator status through the Signal Tap Logic Analyzer and allows you to export status interface so that you can observe the signals through top level design ports or access through user logic.