External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

7.2.5.5. Pin Swizzling

For information on pin swizzling, refer to Configuring DQ Pin Swizzling in the External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide.