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1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide
3.1.1. Agilex™ 7 M-Series EMIF Architecture: I/O Subsystem
3.1.2. Agilex™ 7 M-Series EMIF Architecture: I/O SSM
3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank
3.1.4. Agilex™ 7 M-Series EMIF Architecture: I/O Lane
3.1.5. Agilex™ 7 M-Series EMIF Architecture: Input DQS Clock Tree
3.1.6. Agilex™ 7 M-Series EMIF Architecture: PHY Clock Tree
3.1.7. Agilex™ 7 M-Series EMIF Architecture: PLL Reference Clock Networks
3.1.8. Agilex™ 7 M-Series EMIF Architecture: Clock Phase Alignment
3.1.9. User Clock in Different Core Access Modes
4.1.1. ref_clk for External Memory Interfaces (EMIF) IP
4.1.2. core_init_n for External Memory Interfaces (EMIF) IP
4.1.3. usr_async_clk for External Memory Interfaces (EMIF) IP
4.1.4. usr_clk for External Memory Interfaces (EMIF) IP
4.1.5. usr_rst_n for External Memory Interfaces (EMIF) IP
4.1.6. s0_axi4 for External Memory Interfaces (EMIF) IP
4.1.7. mem for External Memory Interfaces (EMIF) IP
4.1.8. oct for External Memory Interfaces (EMIF) IP
4.2.1. ref_clk for External Memory Interfaces (EMIF) IP
4.2.2. core_init_n for External Memory Interfaces (EMIF) IP
4.2.3. usr_async_clk for External Memory Interfaces (EMIF) IP
4.2.4. usr_clk for External Memory Interfaces (EMIF) IP
4.2.5. usr_rst_n for External Memory Interfaces (EMIF) IP
4.2.6. s0_axi4 for External Memory Interfaces (EMIF) IP
4.2.7. mem for External Memory Interfaces (EMIF) IP
4.2.8. i3c for External Memory Interfaces (EMIF) IP
4.2.9. mem_lbd for External Memory Interfaces (EMIF) IP
4.2.10. mem_lbs for External Memory Interfaces (EMIF) IP
4.2.11. oct for External Memory Interfaces (EMIF) IP
4.3.1. ref_clk for External Memory Interfaces (EMIF) IP
4.3.2. core_init_n for External Memory Interfaces (EMIF) IP
4.3.3. usr_async_clk for External Memory Interfaces (EMIF) IP
4.3.4. usr_clk for External Memory Interfaces (EMIF) IP
4.3.5. usr_rst_n for External Memory Interfaces (EMIF) IP
4.3.6. s0_axi4 for External Memory Interfaces (EMIF) IP
4.3.7. mem for External Memory Interfaces (EMIF) IP
4.3.8. oct for External Memory Interfaces (EMIF) IP
6.2.4.1. Address and Command Pin Placement for DDR4
6.2.4.2. DDR4 Data Width Mapping
6.2.4.3. General Guidelines - DDR4
6.2.4.4. x4 DIMM Implementation
6.2.4.5. Specific Pin Connection Requirements
6.2.4.6. Command and Address Signals
6.2.4.7. Clock Signals
6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3.5.1. Single Rank x 8 Discrete (Component) Topology
6.3.5.2. Single Rank x 16 Discrete (Component) Topology
6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies
6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations
6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations
6.3.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
7.3.1. PCB Stack-up and Design Considerations
7.3.2. General Design Considerations
7.3.3. DDR Differential Signals Routing
7.3.4. Ground Plane and Return Path
7.3.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines
7.3.6. DRAM Break-in Layout Guidelines
7.3.7. DDR5 PCB Layout Guidelines
7.3.8. DDR5 Simulation Strategy
7.3.7.1. DDR5 Discrete Component/Memory Down Topology: up to 40-Bit Interface (1 Rank x8 or x16, 2 Rank x8 or x16)
7.3.7.2. Routing Guidelines for DDR5 Memory Down: 1 Rank or 2 Rank (x8 bit or x16 bit) Configurations
7.3.7.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations
7.3.7.4. Example of a DDR5 layout on an Altera FPGA Platform Board
11.1. Interface Configuration Performance Issues
11.2. Functional Issue Evaluation
11.3. Timing Issue Characteristics
11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer
11.5. Debugging with the External Memory Interface Debug Toolkit
11.6. Generating Traffic with the Test Engine IP
11.7. Guidelines for Developing HDL for Traffic Generator
11.8. Guidelines for Traffic Generator Status Check
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6.3.2. General Layout Routing Guidelines
Follow the guidelines in this section for routing from the FPGA to memory for Agilex™ 7 M-Series devices.
For maximum channel margin, you should consider the following general routing optimizations during the layout design phase:
- The Agilex™ 7 M-Series FPGA EMIF IP for DDR4 does not support a clamshell layout.
- When routing the memory interface, ensure that there are solid ground reference planes without any plane splits or voids, to ensure an uninterrupted current return path.
- For signal vias in layer transitions, you must place ground stitching vias close by, within 80 mil in distance (closer is better), and in between signal vias, to minimize crosstalk among signal vias. Avoid any unnecessary signal layer transitions to minimize crosstalk, loss, and skews.
- Trace impedance plays an important role in signal integrity; board designers must follow impedance recommendations for each signal group and configuration according to the guidelines in this document. If you use a different stackup than the reference stackup in the PCB design, you must tune the trace width and geometries to achieve the impedance recommendations.
- Altera recommends using 45-degree angles (not sharp 90-degree corners) when routing signal turns. Use 3×h spacing for serpentine routing, where h is the height or distance from the trace to the nearest GND reference plane.
- Avoid referencing a signal to both power and ground planes at the same time (dual referencing), for signal return paths. When this cannot be avoided, ensure that the closer reference plane is solid ground, and the far side power plane is not noisy.
- Avoid routing two internal signal layers adjacent to each other (dual stripline routing). When this cannot be avoided, use angled routing between two signal layers to minimize crosstalk and coupling between the layers.
- Follow time-domain length and skew matching rules to ensure that your interface meets timing requirements. You should route signals from the same byte or group together on the same layer to avoid any out-of-phase crosstalk caused by varying layer transition lengths.
- To optimize memory interface margins, Altera recommends the following routing strategies:
- For DIMM configurations, route DQ and DQS signals on shallow layers with short via transition lengths, because they have tighter timing margins than address, command, and control signals. (Shallow layers are those above the PCB core where via transition lengths are short.)
- For discrete device configurations, route address, command, and control signals on shallow layers.
- For boards thicker than 65 mil, Altera recommends alternating adjacent FPGA EMIF BGA/ball rows with deep and shallow board via transitions to minimize crosstalk between adjacent bytes. This method is illustrated in the following figure:
Figure 16. Recommended alternate adjacent via transitions to avoid crosstalk between adjacent bytes
- For boards thicker than 65 mil, using the pin-through-hole (PTH) type of DIMM connector, Altera recommends implementing a loop-routing-around-DIMM-pin structure (Lcomp) to improve impedance matching between signal routing and the DIMM connector. Refer to the following figure.
Figure 17. Recommended Lcomp structure for better impedance matching
- For PCB designs using a surface mount technology (SMT) type of DIMM connector, Altera recommends placing a cutout (void) in the ground reference plane underneath the connector pads for DDR4 signals to minimize connector pad capacitance. Refer to the following figure for the recommended cutout on ground reference plane underneath the connector pad on surface layer.
Figure 18. Recommended Cutout on Ground Reference Plane
Figure 19. Closeup View of Connections
Figure 20. Closeup View of Connections