External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

7.2.4.2. DDR5 Data Width Mapping

The EMIF IP for Agilex™ 7 M-Series devices does not support flexible data lane placement.

Only fixed byte lanes within the I/O bank can be used as data lanes. The following table lists the supported address and command and data lane placements in an I/O bank.

Table 132.  Component
Controller Address Command Scheme Data Width Usage BL7 [P95:P84] BL6 [P83:P72] BL5 [P71:P60] BL4 [P59:P48] BL3 [P47:P36] BL2 [P35:P24] BL1 [P23:P12] BL0 [P11:P0]
Primary Scheme 1 DDR5x16 GPIO GPIO GPIO GPIO AC1 P AC0 P DQ[0] P DQ[1] P
Primary 1 Scheme 1 DDR5x16 DQ[1] P DQ[0] P AC1 P AC0 P X X X GPIO
Primary & Secondary Scheme 1 DDR5 2x16 DQ[1] S DQ[0] S AC1 S AC0 S AC1 P AC0 P DQ[0] P DQ[1] P
Primary Scheme 1 DDR5x16 + ECC GPIO GPIO GPIO DQ[ECC] P AC1 P AC0 P DQ[0] P DQ[1] P
Primary Scheme 1 DDR5x32 GPIO GPIO DQ[3] P DQ[2] P AC1 P AC0 P DQ[0] P DQ[1] P
Primary Scheme 1 DDR5x32 + ECC GPIO DQ[ECC] P DQ[3] P DQ[2] P AC1 P AC0 P DQ[0] P DQ[1] P
Note:
  • P Primary controller.
  • S Secondary controller.
  • 1 ES0 silicon supports this scheme using the primary controller; future revisions will enable the secondary controller, unblocking BL0-3 for GPIO use.
  • X = Not available as GPIO.

DIMM Support

Table 133.  Bank 3A, 3D, 2D
Address Command Scheme Data Width per Channel BL7 [P95:P84] BL6 [P83:P72] BL5 [P71:P60] BL4 [P59:P48] BL3 [P47:P36] BL2 [P35:P24] BL1 [P23:P12] BL0 [P11:P0]
Scheme 1 DDR5 x32 GPIO GPIO DQ[3] P DQ[2] P AC1 P AC[0] P DQ[0] P DQ[1] P
Scheme 1 DDR5 x32 + ECC GPIO DQ[ECC] P DQ[3] P DQ[2] P AC1 P AC[0] P DQ[0] P DQ[1] P
Scheme 2 DDR5 x32 GPIO GPIO DQ[3] P DQ[2] P AC1 P AC[0] P DQ[0] P DQ[1] P
Scheme 2 DDR5 x32 + ECC GPIO DQ[ECC] P DQ[3] P DQ[2] P AC1 P AC[0] P DQ[0] P DQ[1] P
Note: P Primary controller.
Table 134.  Bank 3B, 3C, 2C
Address Command Scheme Data Width per Channel BL7 [P95:P84] BL6 [P83:P72] BL5 [P71:P60] BL4 [P59:P48] BL3 [P47:P36] BL2 [P35:P24] BL1 [P23:P12] BL0 [P11:P0]
Scheme 1 DDR5 x32 DQ[1] P DQ[0] P AC1 P AC0 P DQ[2] P DQ[3] P GPIO 1 GPIO 1
Scheme 1 DDR5 x32 + ECC DQ[1] P DQ[0] P AC1 P AC0 P DQ[2] P DQ[3] P DQ[ECC] P GPIO 1
Scheme 2 DDR5 x32 DQ[1] P DQ[0] P AC1 P AC0 P DQ[2] P DQ[3] P GPIO 1 GPIO 1
Scheme 2 DDR5 x32 + ECC DQ[1] P DQ[0] P AC1 P AC0 P DQ[2] P DQ[3] P DQ[ECC] P GPIO 1
Note:
  • 1 GPIO is available if using NoC access mode.
  • P Primary controller.
  • For banks 3A/3B, 3C/3D, or 2C/2D there are two options available for the address and command placement parameter (AC Placement):
    • Ch0 Top Sub-Bank/Ch1 Bot Sub-Bank, must be selected when placing Ch0 A/C pins in the top sub-bank.
    • Ch0 Bot Sub-Bank/Ch1 Top Sub-Bank, must be selected when placing Ch0 A/C pins in the bottom sub-bank.
Table 135.  Bank 2A
Address Command Scheme Data Width per Channel BL7 [P95:P84] BL6 [P83:P72] BL5 [P71:P60] BL4 [P59:P48] BL3 [P47:P36] BL2 [P35:P24] BL1 [P23:P12] BL0 [P11:P0]
Scheme 1 DDR5 x32 GPIO GPIO DQ[3] P DQ[2] P AC1 P AC0 P DQ[0] P DQ[1] P
Scheme 1 DDR5 x32 + ECC GPIO DQ[ECC] P DQ[3] P DQ[2] P AC1 P AC0 P DQ[0] P DQ[1] P
Scheme 2 DDR5 x32 GPIO GPIO DQ[3] P DQ[2] P AC1 P AC0 P DQ[0] P DQ[1] P
Scheme 2 DDR5 x32 + ECC GPIO DQ[ECC] P DQ[3] P DQ[2] P AC1 P AC0 P DQ[0] P DQ[1] P
Note: P Primary controller.
Table 136.  Bank 2B
Address Command Scheme Data Width per Channel BL7 [P95:P84] BL6 [P83:P72] BL5 [P71:P60] BL4 [P59:P48] BL3 [P47:P36] BL2 [P35:P24] BL1 [P23:P12] BL0 [P11:P0]
Scheme 1 DDR5 x32 GPIO GPIO DQ[3] P DQ[2] P AC1 P AC0 P DQ[0] P DQ[1] P
Scheme 1 DDR5 x32 + ECC GPIO DQ[ECC] P DQ[3] P DQ[2] P AC1 P AC0 P DQ[0] P DQ[1] P
Scheme 2 DDR5 x32 GPIO GPIO DQ[3] P DQ[2] P AC1 P AC0 P DQ[0] P DQ[1] P
Scheme 2 DDR5 x32 + ECC GPIO DQ[ECC] P DQ[3] P DQ[2] P AC1 P AC0 P DQ[0] P DQ[1] P
Note:
  • P Primary controller.
  • For banks 2A and 2B, select Ch0 Bot Sub-Bank/Ch1 Bot Sub-Bank for the address and command placement parameter (AC Placement).