External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support

This chapter contains IP parameter descriptions and pin planning information for Agilex™ 7 M-Series FPGA external memory interface IP for DDR5.