External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

4.1.7. mem for External Memory Interfaces (EMIF) IP

Interface between FPGA and external memory

Table 32.  Interface: memInterface type: conduit
Port Name Direction Description
mem_ck_t output CK Clock (true)
mem_ck_c output CK Clock (complement)
mem_cke output Clock Enable
mem_odt output On-Die Termination
mem_cs_n output Chip Select
mem_c output Chip ID
mem_a output Address
mem_ba output Bank Address
mem_bg output Bank Group
mem_act_n output Activation Command
mem_par output Command/Address Parity (to DDR4 device)
mem_alert_n input Indicates an Address Parity and/or Write CRC Error
mem_reset_n output Asynchronous Reset
mem_dq bidir Data (read/write)
mem_dqs_t bidir Data Strobe (true)
mem_dqs_c bidir Data Strobe (complement)
mem_dbi_n bidir Acts as either the data bus inversion pin, or the data mask pin, depending on the configuration and whether it's a read or write transaction