External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

4.1.5. usr_rst_n for External Memory Interfaces (EMIF) IP

User clock domain reset interface

Table 30.  Interface: usr_rst_nInterface type: reset
Port Name Direction Description
usr_rst_n output User reset