External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

8.2.4.1. Address and Command Pin Placement for LPDDR5

Agilex™ 7 M-Series FPGA LPDDR5 IP supports fixed address and command pin placement as shown in the following table. The IP supports up to 2 ranks.

Table 174.  Address and Command Pin Placement
Address/Command Lane Index Within Byte Lane LPDDR5
AC1 11  
10  
9  
8 CS_N[1]
7 CK_C[0]
6 CK_T[0]
5 CS_N[0]
4 CA[6]
3 RESET_N
2 RZQ Site
1  
0  
AC0 11 Differential "N-Side" reference clock input site
10 Differential "P-Side" reference clock input site
9 CA[5]
8 CA[4]
7 WCK_C[1]
6 WCK_T[1]
5 WCK_C[0]
4 WCK_T[0]
3 CA[3]
2 CA[2]
1 CA[1]
0 CA[0]