External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

11.8.1. Status Check Using the Signal Tap Logic Analyzer

When you generate an Agilex™ 7 FPGA EMIF IP design example, you can specify the traffic pattern to run. Select the required setting, as illustrated in the figure below.

Figure 83. Selecting Traffic Generator Pattern

Refer to the External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide for more information.

Observing Status with the Signal Tap Logic Analyzer

Follow these steps to observe status using the Signal Tap Logic Analyzer:

  1. Generate a Signal Tap Logic Analyzer file, which includes traffic generator status signals.
    Figure 84. 
    Note: The status_done and status_error ports on the traffic_generator|hydra_inst|global_csr instance are the traffic generator status signals.
  2. Save and enable the Signal Tap file in the project, and recompile the design.
  3. Configure the device with your .sof file and observe the signals status through signal tap file.
  4. Signal values of status_done=1 and status_error=0 indicate that the traffic test completed with no traffic errors.
    Figure 85. 
    Note: For an infinite traffic pattern program, you will not see status_done=1, because the traffic continues running. Set the trigger conditions at the rising edge of the status_error signal and let the traffic run. Any failure in traffic is detected if the status_error signal goes high.