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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
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6.8.2. XGMII RX Signals
Signal | Condition | Direction | Width | Description |
---|---|---|---|---|
xgmii_rx_data[] | Use legacy Ethernet 10G MAC XGMII interface disabled. |
In | 32 | 4-lane RX data bus. Lane 0 starts from the least significant bit.
|
xgmii_rx_control[] | Use legacy Ethernet 10G MAC XGMII interface disabled. |
In | 4 | Control bits for each lane in xgmii_rx_data[].
|
xgmii_rx_valid | Use legacy Ethernet 10G MAC XGMII interface disabled. |
In | 1 | XGMII RX valid signal. When asserted, indicates that the data and control buses are valid. |
link_fault_status_xgmii_rx_data[] | — | Out | 2 | The following values indicate the link fault status:
|